[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240918205319.3517569-5-coltonlewis@google.com>
Date: Wed, 18 Sep 2024 20:53:17 +0000
From: Colton Lewis <coltonlewis@...gle.com>
To: kvm@...r.kernel.org
Cc: Mingwei Zhang <mizhang@...gle.com>, Jinrong Liang <ljr.kernel@...il.com>,
Jim Mattson <jmattson@...gle.com>, Aaron Lewis <aaronlewis@...gle.com>,
Sean Christopherson <seanjc@...gle.com>, Paolo Bonzini <pbonzini@...hat.com>, Shuah Khan <shuah@...nel.org>,
linux-kselftest@...r.kernel.org, linux-kernel@...r.kernel.org,
Colton Lewis <coltonlewis@...gle.com>
Subject: [PATCH v2 4/6] KVM: x86: selftests: Test read/write core counters
Run a basic test to ensure we can write an arbitrary value to the core
counters and read it back.
Signed-off-by: Colton Lewis <coltonlewis@...gle.com>
---
.../selftests/kvm/x86_64/pmu_counters_test.c | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
index 5b240585edc5..79ca7d608e00 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c
@@ -641,11 +641,65 @@ static uint8_t nr_core_counters(void)
return AMD_NR_CORE_EXT_COUNTERS;
return AMD_NR_CORE_COUNTERS;
+}
+
+static uint8_t guest_nr_core_counters(void)
+{
+ uint8_t nr_counters = this_cpu_property(X86_PROPERTY_NUM_PERF_CTR_CORE);
+ bool core_ext = this_cpu_has(X86_FEATURE_PERF_CTR_EXT_CORE);
+
+ if (nr_counters != 0)
+ return nr_counters;
+
+ if (core_ext)
+ return AMD_NR_CORE_EXT_COUNTERS;
+
+ return AMD_NR_CORE_COUNTERS;
+
+}
+static void guest_test_rdwr_core_counters(void)
+{
+ bool core_ext = this_cpu_has(X86_FEATURE_PERF_CTR_EXT_CORE);
+ uint8_t nr_counters = guest_nr_core_counters();
+ uint8_t i;
+ uint32_t esel_msr_base = core_ext ? MSR_F15H_PERF_CTL : MSR_K7_EVNTSEL0;
+ uint32_t cnt_msr_base = core_ext ? MSR_F15H_PERF_CTR : MSR_K7_PERFCTR0;
+ uint32_t msr_step = core_ext ? 2 : 1;
+
+ for (i = 0; i < AMD_NR_CORE_EXT_COUNTERS; i++) {
+ uint64_t test_val = 0xffff;
+ uint32_t esel_msr = esel_msr_base + msr_step * i;
+ uint32_t cnt_msr = cnt_msr_base + msr_step * i;
+ bool expect_gp = !(i < nr_counters);
+ uint8_t vector;
+ uint64_t val;
+
+ /* Test event selection register. */
+ vector = wrmsr_safe(esel_msr, test_val);
+ GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, esel_msr, expect_gp, vector);
+
+ vector = rdmsr_safe(esel_msr, &val);
+ GUEST_ASSERT_PMC_MSR_ACCESS(RDMSR, esel_msr, expect_gp, vector);
+
+ if (!expect_gp)
+ GUEST_ASSERT_PMC_VALUE(RDMSR, esel_msr, val, test_val);
+
+ /* Test counter register. */
+ vector = wrmsr_safe(cnt_msr, test_val);
+ GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, cnt_msr, expect_gp, vector);
+
+ vector = rdmsr_safe(cnt_msr, &val);
+ GUEST_ASSERT_PMC_MSR_ACCESS(RDMSR, cnt_msr, expect_gp, vector);
+
+ if (!expect_gp)
+ GUEST_ASSERT_PMC_VALUE(RDMSR, cnt_msr, val, test_val);
+ }
}
static void guest_test_core_counters(void)
{
+ guest_test_rdwr_core_counters();
GUEST_DONE();
}
--
2.46.0.662.g92d0881bb0-goog
Powered by blists - more mailing lists