[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20240919-topic-apps_smmu_coherent-v1-5-5b3a8662403d@quicinc.com>
Date: Thu, 19 Sep 2024 00:57:18 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, cros-qcom-dts-watchers@...omium.org
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Konrad Dybcio <quic_kdybcio@...cinc.com>
Subject: [PATCH RFC 05/11] arm64: dts: qcom: sdm670: Affirm IDR0.CCTW on
apps_smmu
From: Konrad Dybcio <quic_kdybcio@...cinc.com>
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@...cinc.com>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 187c6698835d34e617aeb83309b6d5926eb57198..a08a64bc033ffdea283645c6bf4ed835a59c3366 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1737,6 +1737,7 @@ apps_smmu: iommu@...00000 {
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
};
gladiator_noc: interconnect@...00000 {
--
2.46.1
Powered by blists - more mailing lists