linux-kernel - Re: [PATCH v3 6/6] gpio: aspeed: Add the flush write to ensure the write complete.

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Message-ID:
 <OSQPR06MB7252E3D6D693BB5A920EFE798B632@OSQPR06MB7252.apcprd06.prod.outlook.com>
Date: Thu, 19 Sep 2024 06:07:10 +0000
From: Billy Tsai <billy_tsai@...eedtech.com>
To: Andrew Jeffery <andrew@...econstruct.com.au>, "linus.walleij@...aro.org"
	<linus.walleij@...aro.org>, "brgl@...ev.pl" <brgl@...ev.pl>,
	"robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
	"joel@....id.au" <joel@....id.au>, "linux-gpio@...r.kernel.org"
	<linux-gpio@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-aspeed@...ts.ozlabs.org"
	<linux-aspeed@...ts.ozlabs.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, BMC-SW <BMC-SW@...eedtech.com>,
	"Peter.Yin@...ntatw.com" <Peter.Yin@...ntatw.com>
Subject: Re: [PATCH v3 6/6] gpio: aspeed: Add the flush write to ensure the
 write complete.

> > Performing a dummy read ensures that the register write operation is fully
> > completed, mitigating any potential bus delays that could otherwise impact
> > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to
> > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application
> > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on
> > a delay function to ensure the clock frequency does not exceed 1 MHz.
> > However, this can lead to rapid toggling of the GPIO because the write
> > operation is POSTed and does not wait for a bus acknowledgment.
> >
> > Signed-off-by: Billy Tsai <billy_tsai@...eedtech.com>

> ... are you aware of any other driver concerns of a similar nature wrt
> the architecture of the SoCs?

No, we are only aware of this issue with the GPIO controller, which affects
the output pin behavior immediately after register write.