linux-kernel - Re: [PATCH v2 0/5] Add support for PCIe3 on x1e80100

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6f1118eb-89cf-4fd4-a35d-e8b98b0b7a8d@quicinc.com>
Date: Thu, 19 Sep 2024 22:14:06 +0800
From: Qiang Yu <quic_qianyu@...cinc.com>
To: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>,
        <manivannan.sadhasivam@...aro.org>, <vkoul@...nel.org>,
        <kishon@...nel.org>, <robh@...nel.org>, <andersson@...nel.org>,
        <konradybcio@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <mturquette@...libre.com>, <sboyd@...nel.org>, <abel.vesa@...aro.org>,
        <quic_msarkar@...cinc.com>, <quic_devipriy@...cinc.com>
CC: <dmitry.baryshkov@...aro.org>, <kw@...ux.com>, <lpieralisi@...nel.org>,
        <neil.armstrong@...aro.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-phy@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v2 0/5] Add support for PCIe3 on x1e80100


On 9/14/2024 11:59 AM, Krishna Chaitanya Chundru wrote:
> Hi qiang,
>
> In next series can you add logic in controller driver
> to have new ops for this x1e80100 since this hardware
> has smmuv3 support but currently the ops_1_9_0 ops which
> is being used has configuring bdf to sid table which will
> be not present for this devices.
>
Sure, bdf2sid map is not supported and required since we use smmuv3 for
pcie on x1e80100. Can I add a new ops which is same as ops_1_9_0 basically
and only config_sid callback is removed. Or add a new flag to determine if
we need to config bdf2sid map like no_l0s.

Hi Mani, what do you think about this?

Thanks,
Qiang
>
> - Krishna Chaitanya.
>
> On 9/13/2024 2:07 PM, Qiang Yu wrote:
>> This series add support for PCIe3 on x1e80100.
>>
>> PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP
>> PHY configuration compare other PCIe instances on x1e80100. Hence add
>> required resource configuration and usage for PCIe3.
>>
>> v2->v1:
>> 1. Squash [PATCH 1/8], [PATCH 2/8],[PATCH 3/8] into one patch and 
>> make the
>>     indentation consistent.
>> 2. Put dts patch at the end of the patchset.
>> 3. Put dt-binding patch at the first of the patchset.
>> 4. Add a new patch where opp-table is added in dt-binding to avoid dtbs
>>     checking error.
>> 5. Remove GCC_PCIE_3_AUX_CLK, RPMH_CXO_CLK, put in 
>> TCSR_PCIE_8L_CLKREF_EN
>>     as ref.
>> 6. Remove lane_broadcasting.
>> 7. Add 64 bit bar, Remove GCC_PCIE_3_PIPE_CLK_SRC,
>>     GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK is changed to
>>     GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK.
>> 8. Add Reviewed-by tag.
>> 9. Remove [PATCH 7/8], [PATCH 8/8].
>>
>> Qiang Yu (5):
>>    dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100
>>      QMP PCIe PHY Gen4 x8
>>    dt-bindings: PCI: qcom: Add OPP table for X1E80100
>>    phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3
>>    clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks
>>    arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100
>>
>>   .../bindings/pci/qcom,pcie-x1e80100.yaml      |   4 +
>>   .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml       |   3 +
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi        | 202 ++++++++++++++++-
>>   drivers/clk/qcom/gcc-x1e80100.c               |  10 +-
>>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c      | 211 ++++++++++++++++++
>>   .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h    |  25 +++
>>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h |  19 ++
>>   7 files changed, 468 insertions(+), 6 deletions(-)
>>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h
>>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h
>>