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Message-Id: <20240919-pcie_ep_range-v1-3-b3e9d62780b7@nxp.com>
Date: Thu, 19 Sep 2024 18:03:03 -0400
From: Frank Li <Frank.Li@....com>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>, 
 Krzysztof Wilczyński <kw@...ux.com>, 
 Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, 
 Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Abraham I <kishon@...nel.org>, 
 Saravana Kannan <saravanak@...gle.com>, Jingoo Han <jingoohan1@...il.com>, 
 Gustavo Pimentel <gustavo.pimentel@...opsys.com>, 
 Jesper Nilsson <jesper.nilsson@...s.com>, 
 Richard Zhu <hongxing.zhu@....com>, Lucas Stach <l.stach@...gutronix.de>, 
 Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>, 
 Pengutronix Kernel Team <kernel@...gutronix.de>, 
 Fabio Estevam <festevam@...il.com>
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, linux-arm-kernel@...s.com, 
 linux-arm-kernel@...ts.infradead.org, imx@...ts.linux.dev, 
 Krzysztof Wilczyński <kwilczynski@...nel.org>, 
 Frank Li <Frank.Li@....com>
Subject: [PATCH 3/9] of: address: Add device type pci-ep

The PCI bus device tree supports 'ranges' properties that indicate how to
convert PCI addresses to CPU addresses. Many PCI controllers are dual-role
controllers, supporting both Root Complex (RC) and Endpoint (EP) modes. The
EP side also needs similar information for proper address translation.

Add device type 'pci-ep' and use the same PCI address parser function to
parser PCI EP's ranges property.

Signed-off-by: Frank Li <Frank.Li@....com>
---
 drivers/of/address.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/of/address.c b/drivers/of/address.c
index d886f16df8a6e..c98e212d53dc1 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -117,13 +117,13 @@ static int of_bus_default_flags_translate(__be32 *addr, u64 offset, int na)
 	return of_bus_default_translate(addr + 1, offset, na - 1);
 }
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI_ENDPOINT)
 static unsigned int of_bus_pci_get_flags(const __be32 *addr)
 {
 	unsigned int flags = 0;
 	u32 w = be32_to_cpup(addr);
 
-	if (!IS_ENABLED(CONFIG_PCI))
+	if (!IS_ENABLED(CONFIG_PCI) && !IS_ENABLED(CONFIG_PCI_ENDPOINT))
 		return 0;
 
 	switch((w >> 24) & 0x03) {
@@ -172,6 +172,11 @@ static int of_bus_pci_match(struct device_node *np)
 		of_node_is_pcie(np, "pcie");
 }
 
+static int of_bus_pci_ep_match(struct device_node *np)
+{
+	return of_node_is_type(np, "pci-ep") || of_node_is_pcie(np, "pcie-ep");
+}
+
 static void of_bus_pci_count_cells(struct device_node *np,
 				   int *addrc, int *sizec)
 {
@@ -196,7 +201,7 @@ static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns,
 	return of_bus_default_map(addr, range, na, ns, pna, fna);
 }
 
-#endif /* CONFIG_PCI */
+#endif /* CONFIG_PCI || CONFIG_PCI_ENDPOINT */
 
 static int __of_address_resource_bounds(struct resource *r, u64 start, u64 size)
 {
@@ -354,6 +359,19 @@ static struct of_bus of_busses[] = {
 		.get_flags = of_bus_pci_get_flags,
 	},
 #endif /* CONFIG_PCI */
+#ifdef CONFIG_PCI_ENDPOINT
+	/* PCI Endpoint */
+	{
+		.name = "pci-ep",
+		.addresses = "assigned-addresses",
+		.match = of_bus_pci_ep_match,
+		.count_cells = of_bus_pci_count_cells,
+		.map = of_bus_pci_map,
+		.translate = of_bus_default_flags_translate,
+		.flag_cells = 1,
+		.get_flags = of_bus_pci_get_flags,
+	},
+#endif /* CONFIG_PCI_EP */
 	/* ISA */
 	{
 		.name = "isa",

-- 
2.34.1


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