linux-kernel - Re: [PATCH RFC 02/11] arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps

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Message-ID: <CAD=FV=Xrbe1NO+trk1SJ30gHm5jLFjd0bAeG3H46gD+vNFZa1w@mail.gmail.com>
Date: Fri, 20 Sep 2024 06:44:53 -0700
From: Doug Anderson <dianders@...omium.org>
To: Konrad Dybcio <konradybcio@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	cros-qcom-dts-watchers@...omium.org, 
	Marijn Suijten <marijn.suijten@...ainline.org>, linux-arm-msm@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Konrad Dybcio <quic_kdybcio@...cinc.com>, Rob Clark <robdclark@...il.com>
Subject: Re: [PATCH RFC 02/11] arm64: dts: qcom: sc7180: Affirm IDR0.CCTW on apps_smmu

Hi,

On Wed, Sep 18, 2024 at 3:58 PM 'Konrad Dybcio' via
cros-qcom-dts-watchers <cros-qcom-dts-watchers@...omium.org> wrote:
>
> From: Konrad Dybcio <quic_kdybcio@...cinc.com>
>
> On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent

FWIW, the "RPMh-based" confused me a bit. This isn't really related to
RPMh, right? I think you're just using "RPMh-based" to establish a
point in time and that Qualcomm added RPMh in the same generation of
SoCs that they added cache-coherent pagetable walk?


> pagetable walk via the IDR0 register. This however is not respected by
> the arm-smmu driver unless dma-coherent is set.
>
> Mark the node as dma-coherent to ensure this (and other) implementations
> take this coherency into account.
>
> Signed-off-by: Konrad Dybcio <quic_kdybcio@...cinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
>  1 file changed, 1 insertion(+)

I remotely booted this on sc7180-trogdor-lazor. Since I'm working
remotely at the moment I can't check the screen, but I can at least
confirm that nothing seemed to go boom. I can also confirm that
without your patch I see:

[    1.580607] arm-smmu 15000000.iommu:         non-coherent table walk
[    1.580612] arm-smmu 15000000.iommu:         (IDR0.CTTW overridden
by FW configuration)

...and after your patch I see:

[    1.569350] arm-smmu 15000000.iommu:         coherent table walk

Thus:

Tested-by: Douglas Anderson <dianders@...omium.org>

I'm curious: can this also be turned on for the Adreno SMMU also?
dmesg still has this after your patch (which makes sense since your
patch didn't touch the Adreno SMMU):

[    2.423521] arm-smmu 5040000.iommu:  non-coherent table walk
[    2.423526] arm-smmu 5040000.iommu:  (IDR0.CTTW overridden by FW
configuration)

-Doug