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Message-Id: <20240921-msm-mdss-ubwc-v1-2-411dcf309d05@linaro.org>
Date: Sat, 21 Sep 2024 11:17:30 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org
Subject: [PATCH 2/4] drm/msm/mdss: use register definitions instead of
hand-coding them
Move existing register definitions to mdss.xml and use generated defines
for registers access instead of hand-coding everything in the source
file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
---
drivers/gpu/drm/msm/msm_mdss.c | 35 +++++++++++---------------
drivers/gpu/drm/msm/registers/display/mdss.xml | 6 +++++
2 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index faa88fd6eb4d..ca9b7f953ac4 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -19,13 +19,7 @@
#include "msm_mdss.h"
#include "msm_kms.h"
-#define HW_REV 0x0
-#define HW_INTR_STATUS 0x0010
-
-#define UBWC_DEC_HW_VERSION 0x58
-#define UBWC_STATIC 0x144
-#define UBWC_CTRL_2 0x150
-#define UBWC_PREDICTION_MODE 0x154
+#include <generated/mdss.xml.h>
#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
@@ -83,7 +77,7 @@ static void msm_mdss_irq(struct irq_desc *desc)
chained_irq_enter(chip, desc);
- interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS);
+ interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS);
while (interrupts) {
irq_hw_number_t hwirq = fls(interrupts) - 1;
@@ -173,7 +167,7 @@ static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
{
const struct msm_mdss_data *data = msm_mdss->mdss_data;
- writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC);
+ writel_relaxed(data->ubwc_static, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
}
static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
@@ -189,7 +183,7 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
if (data->ubwc_enc_version == UBWC_1_0)
value |= BIT(8);
- writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
+ writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
}
static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
@@ -200,21 +194,22 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
(data->highest_bank_bit & 0x7) << 4 |
(data->macrotile_mode & 0x1) << 12;
- writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
+ writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
if (data->ubwc_enc_version == UBWC_3_0) {
- writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
- writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
+ writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
+ writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
} else {
if (data->ubwc_dec_version == UBWC_4_3)
- writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2);
+ writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
else
- writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
- writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
+ writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
+ writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
}
}
-#define MDSS_HW_MAJ_MIN GENMASK(31, 16)
+#define MDSS_HW_MAJ_MIN \
+ (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK)
#define MDSS_HW_MSM8996 0x1007
#define MDSS_HW_MSM8937 0x100e
@@ -235,7 +230,7 @@ static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_m
if (!data)
return NULL;
- hw_rev = readl_relaxed(mdss->mmio + HW_REV);
+ hw_rev = readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION);
hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev);
if (hw_rev == MDSS_HW_MSM8996 ||
@@ -334,9 +329,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
msm_mdss->mdss_data->ubwc_dec_version);
dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",
- readl_relaxed(msm_mdss->mmio + HW_REV));
+ readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION));
dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
- readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));
+ readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION));
break;
}
diff --git a/drivers/gpu/drm/msm/registers/display/mdss.xml b/drivers/gpu/drm/msm/registers/display/mdss.xml
index 9354cfffb730..ac85caf1575c 100644
--- a/drivers/gpu/drm/msm/registers/display/mdss.xml
+++ b/drivers/gpu/drm/msm/registers/display/mdss.xml
@@ -18,6 +18,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<bitfield name="INTR_HDMI" pos="8" type="boolean"/>
<bitfield name="INTR_EDP" pos="12" type="boolean"/>
</reg32>
+
+ <reg32 offset="0x00058" name="UBWC_DEC_HW_VERSION"/>
+
+ <reg32 offset="0x00144" name="UBWC_STATIC"/>
+ <reg32 offset="0x00150" name="UBWC_CTRL_2"/>
+ <reg32 offset="0x00154" name="UBWC_PREDICTION_MODE"/>
</domain>
</database>
--
2.39.5
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