linux-kernel - [PATCH 2/5] clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core

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Message-ID: <9f8d4e5e-963e-4717-9a28-9181ea662024@marvell.com>
Date: Mon, 23 Sep 2024 02:39:15 +0530
From: Amit Singh Tomar <amitsinght@...vell.com>
To: Pablo Sun <pablo.sun@...iatek.com>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd
 <sboyd@...nel.org>,
        Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org
Subject: [PATCH 2/5] clk: mediatek: clk-mt8188-topckgen: Remove univpll from
 parents of mfg_core_tmp

Hi,

> Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated
> mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when
> setting mfgpll clock rate.
> 
> If we keep the univpll parents from mfg_core_tmp, when setting
> GPU frequency to 390000000, the common clock framework would switch
> the parent to univpll, instead of setting mfgpll to 390000000:
> 
>       mfgpll                            0        0        0   949999756
>       univpll                           2        2        0  2340000000
>          univpll_d6                     1        1        0   390000000
>             top_mfg_core_tmp            1        1        0   390000000
>                mfg_ck_fast_ref          1        1        0   390000000
>                   mfgcfg_bg3d           1        1        0   390000000
> 
> This results in failures when subsequent devfreq operations need to
> switch to other frequencies. So remove univpll from the parent list.
> 
> This solution is taken from commit 72d38ed720e9 ("clk: mediatek:
> clk-mt8195-topckgen: Drop univplls from mfg mux parents")
> 
> Signed-off-by: Pablo Sun <pablo.sun@...iatek.com>
> ---
>    drivers/clk/mediatek/clk-mt8188-topckgen.c | 7 +++++--
>    1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> index 2ccc8a1c98f9..74ee692ac613 100644
> --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c
> +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> @@ -342,11 +342,14 @@ static const char * const dsp7_parents[] = {
>    	"univpll_d3"
>    };
>    
> +/*
> + * MFG can be also parented to "univpll_d6" and "univpll_d7":
> + * these have been removed from the parents list to let us
> + * achieve GPU DVFS without any special clock handlers.
> + */
>    static const char * const mfg_core_tmp_parents[] = {
>    	"clk26m",
>    	"mainpll_d5_d2",
nit: Comma at the end of mainpll_d5_d2 is unnecessary.
> -	"univpll_d6",
> -	"univpll_d7"
>    };
>    
>    static const char * const camtg_parents[] = {
> -- 
> 2.45.2
> 
>