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Message-ID: <ffc1900b-3921-48ca-a2b2-1b798c57e572@collabora.com>
Date: Tue, 24 Sep 2024 13:42:01 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Macpaul Lin <macpaul.lin@...iatek.com>,
Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Yong Wu <yong.wu@...iatek.com>,
Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Matthias Brugger <matthias.bgg@...il.com>, dri-devel@...ts.freedesktop.org,
linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, iommu@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
Alexandre Mergnat <amergnat@...libre.com>
Cc: Bear Wang <bear.wang@...iatek.com>, Pablo Sun <pablo.sun@...iatek.com>,
Macpaul Lin <macpaul@...il.com>, Sen Chu <sen.chu@...iatek.com>,
Chris-qj chen <chris-qj.chen@...iatek.com>,
MediaTek Chromebook Upstream
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Chen-Yu Tsai <wenst@...omium.org>
Subject: Re: [PATCH 3/6] dt-bindings: display: mediatek: Fix clocks count
constraint for new SoCs
Il 24/09/24 12:31, Macpaul Lin ha scritto:
> The display node in mt8195.dtsi was triggering a CHECK_DTBS error due
> to an excessively long 'clocks' property:
> display@...06000: clocks: [[31, 14], [31, 43], [31, 44]] is too long
>
> To resolve this issue, add "maxItems: 3" to the 'clocks' property in
> the DT schema.
>
> Fixes: 4ed545e7d100 ("dt-bindings: display: mediatek: disp: split each block to individual yaml")
> Signed-off-by: Macpaul Lin <macpaul.lin@...iatek.com>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,split.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> index e4affc854f3d..42d2d483cc29 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> @@ -57,6 +57,7 @@ properties:
> clocks:
> items:
> - description: SPLIT Clock
That's at least confusing (granted that it works) - either add a description for
each clock and then set `minItems: 1` (preferred), or remove this "SPLIT Clock"
description and allow a maximum of 3 clocks.
Removing the description can be done - IMO - because "SPLIT Clock" is, well,
saying that the SPLIT block gets a SPLIT clock ... stating the obvious, anyway.
Cheers,
Angelo
> + maxItems: 3
>
> required:
> - compatible
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