linux-kernel - Re: [PATCH 1/2] arm64: dts: qcom: x1e80100-crd: Enable external DP support

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Message-ID: <CAA8EJpq1WwmJfZdW7e3EWEucHpnEYZJkFOek65YcadYwgXWyCg@mail.gmail.com>
Date: Tue, 24 Sep 2024 14:03:13 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Abel Vesa <abel.vesa@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konradybcio@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Johan Hovold <johan@...nel.org>, Neil Armstrong <neil.armstrong@...aro.org>, 
	Trilok Soni <quic_tsoni@...cinc.com>, linux-arm-msm@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] arm64: dts: qcom: x1e80100-crd: Enable external DP support

On Tue, 24 Sept 2024 at 13:08, Abel Vesa <abel.vesa@...aro.org> wrote:
>
> On 24-09-02 21:54:58, Dmitry Baryshkov wrote:
> > On Mon, Sep 02, 2024 at 06:01:35PM GMT, Abel Vesa wrote:
> > > The Qualcomm Snapdragon X Elite CRD board has 3 USB Type-C ports,
> > > all of them supporting external DP altmode. Between each QMP
> > > combo PHY and the corresponding Type-C port, sits one Parade PS8830
> > > retimer which handles both orientation and SBU muxing. Add nodes for
> > > each retimer, fix the graphs between connectors and the PHYs accordingly,
> > > add the voltage regulators needed by each retimer and then enable all
> > > 3 remaining DPUs.
> > >
> > > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > > ---
> > >  arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 414 +++++++++++++++++++++++++++++-
> > >  1 file changed, 408 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> > > index 10b28d870f08..6dfc85eda354 100644
> > > --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> > > +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
> >
> > [skipped]
> >
> >
> > > @@ -709,6 +861,163 @@ keyboard@3a {
> > >     };
> > >  };
> > >
> > > +&i2c1 {
> > > +   clock-frequency = <400000>;
> > > +
> > > +   status = "okay";
> > > +
> > > +   typec-mux@8 {
> > > +           compatible = "parade,ps8830";
> > > +           reg = <0x08>;
> > > +
> > > +           clocks = <&rpmhcc RPMH_RF_CLK5>;
> > > +           clock-names = "xo";
> > > +
> > > +           vdd15-supply = <&vreg_rtmr2_1p15>;
> > > +           vdd18-supply = <&vreg_rtmr2_1p8>;
> > > +           vdd33-supply = <&vreg_rtmr2_3p3>;
> > > +
> > > +           reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>;
> > > +
> > > +           orientation-switch;
> > > +           retimer-switch;
> >
> > Doesn't it need to listen to mode switching events? 4-lane DP vs
> > 2/2-lane DP + USB3 requires propagating of the altmode events to the QMP
> > PHY, see the original 4-lane series.
>
> The mode is passed through the retimer state as well, isn't it?

ack.

>
> >
> > > +
> > > +           ports {
> > > +                   #address-cells = <1>;
> > > +                   #size-cells = <0>;
> > > +
> > > +                   port@0 {
> > > +                           reg = <0>;
> > > +
> > > +                           retimer_ss2_ss_out: endpoint {
> > > +                                   remote-endpoint = <&pmic_glink_ss2_ss_in>;
> > > +                           };
> > > +                   };
> > > +
> > > +                   port@1 {
> > > +                           reg = <1>;
> > > +
> > > +                           retimer_ss2_ss_in: endpoint {
> > > +                                   remote-endpoint = <&usb_1_ss2_qmpphy_out>;
> > > +                           };
> > > +                   };
> > > +
> > > +                   port@2 {
> > > +                           reg = <2>;
> > > +
> > > +                           retimer_ss2_con_sbu_out: endpoint {
> > > +                                   remote-endpoint = <&pmic_glink_ss2_con_sbu_in>;
> > > +                           };
> > > +                   };
> > > +           };
> > > +   };
> > > +};
> > > +
> >
> >
> > > @@ -1164,7 +1566,7 @@ &usb_1_ss0_dwc3_hs {
> > >  };
> > >
> > >  &usb_1_ss0_qmpphy_out {
> > > -   remote-endpoint = <&pmic_glink_ss0_ss_in>;
> > > +   remote-endpoint = <&retimer_ss0_ss_in>;
> > >  };
> >
> > orientation-switch and mode-switch for the QMP PHY?
>
> orientation-switch is already in the SoC dtsi nodes.
>
> But the qmp phy doesn't currently support mode switching. Right?

Yeah, we didn't land that patchset :-(

>
> >
> > >
> > >  &usb_1_ss1_hsphy {
> > > @@ -1196,7 +1598,7 @@ &usb_1_ss1_dwc3_hs {
> > >  };
> > >
> > >  &usb_1_ss1_qmpphy_out {
> > > -   remote-endpoint = <&pmic_glink_ss1_ss_in>;
> > > +   remote-endpoint = <&retimer_ss1_ss_in>;
> > >  };
> > >
> > >  &usb_1_ss2_hsphy {
> > > @@ -1228,5 +1630,5 @@ &usb_1_ss2_dwc3_hs {
> > >  };
> > >
> > >  &usb_1_ss2_qmpphy_out {
> > > -   remote-endpoint = <&pmic_glink_ss2_ss_in>;
> > > +   remote-endpoint = <&retimer_ss2_ss_in>;
> > >  };
> > >
> > > --
> > > 2.34.1
> > >
> >
> > --
> > With best wishes
> > Dmitry
>
> Thanks for reviewing.
>
> Abel



-- 
With best wishes
Dmitry