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Message-ID: <20240924142018.6ya5jtdxcgpunnvq@thinkpad>
Date: Tue, 24 Sep 2024 16:20:18 +0200
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Thippeswamy Havalige <thippesw@....com>
Cc: kw@...ux.com, robh@...nel.org, bhelgaas@...gle.com,
	devicetree@...r.kernel.org, conor+dt@...nel.org, krzk+dt@...nel.org,
	bharat.kumar.gogada@....com, michal.simek@....com,
	lpieralisi@...nel.org, linux-pci@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible
 string for CPM5 host1

On Sun, Sep 22, 2024 at 11:43:17AM +0530, Thippeswamy Havalige wrote:
> The Xilinx Versal premium series has CPM5 block which supports two typeA
> Root Port controller functionality at Gen5 speed.
> 
> Add compatible string to distinguish between two CPM5 rootport controller1.
> since Legacy and error interrupt register and bits for both the controllers
> are at different offsets.
> 
> Signed-off-by: Thippeswamy Havalige <thippesw@....com>

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>

- Mani

> ---
> changes in v3:
> --------------
> 1. Modify compatible string.
> ---
>  Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> index 989fb0fa2577..b63a759ec2d7 100644
> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> @@ -17,6 +17,7 @@ properties:
>      enum:
>        - xlnx,versal-cpm-host-1.00
>        - xlnx,versal-cpm5-host
> +      - xlnx,versal-cpm5-host1
>  
>    reg:
>      items:
> -- 
> 2.34.1
> 

-- 
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