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Message-ID: <CAPYmKFs7s4fHBEZCuE92hwVPCTwvUX3864tR5OmgBKkMY57BKg@mail.gmail.com>
Date: Wed, 25 Sep 2024 23:04:09 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: Andreas Schwab <schwab@...e.de>
Cc: Andrew Jones <ajones@...tanamicro.com>, paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, andy.chiu@...ive.com, guoren@...nel.org,
christoph.muellner@...ll.eu, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, lihangjing@...edance.com,
dengliang.1214@...edance.com, xieyongji@...edance.com,
chaiwen.cc@...edance.com
Subject: Re: [External] Re: [PATCH v3 1/2] riscv: process: Introduce idle
thread using Zawrs extension
Hi Andreas,
Thanks a lot for your reply.
On Wed, Sep 25, 2024 at 10:10 PM Andreas Schwab <schwab@...e.de> wrote:
>
> On Sep 25 2024, Andrew Jones wrote:
>
> > On Wed, Sep 25, 2024 at 09:15:46PM GMT, Xu Lu wrote:
> >> @@ -148,6 +149,21 @@ static inline void wait_for_interrupt(void)
> >> __asm__ __volatile__ ("wfi");
> >> }
> >>
> >> +static inline void wrs_nto(unsigned long *addr)
> >> +{
> >> + int val;
> >> +
> >> + __asm__ __volatile__(
> >> +#ifdef CONFIG_64BIT
> >> + "lr.d %[p], %[v]\n\t"
> >> +#else
> >> + "lr.w %[p], %[v]\n\t"
> >> +#endif
> >
> > val is always 32-bit since it's an int. We should always use lr.w.
>
> Shouldn't val be unsigned long like the pointer that is being read?
Yes. As I replied Andrew, the 'int val' is a mistake here. The val can
be an unsigned long (thread_info->flags) when CONFIG_SMP is disabled.
I will update the declaration of val from 'int' to 'unsigned long'.
>
> --
> Andreas Schwab, SUSE Labs, schwab@...e.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
Thanks,
Xu Lu.
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