linux-kernel - [PATCH 0/2] irqchip/ocelot: Fix trigger register address

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Message-Id: <20240925184416.54204-1-matsievskiysv@gmail.com>
Date: Wed, 25 Sep 2024 21:44:14 +0300
From: Sergey Matsievskiy <matsievskiysv@...il.com>
To: tglx@...utronix.de
Cc: maz@...nel.org,
	alexandre.belloni@...tlin.com,
	gregory.clement@...tlin.com,
	lars.povlsen@...rochip.com,
	UNGLinuxDriver@...rochip.com,
	linux-mips@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Sergey Matsievskiy <matsievskiysv@...il.com>
Subject: [PATCH 0/2] irqchip/ocelot: Fix trigger register address

Use main interrupt trigger registers instead of device interrupt trigger
registers.

Controllers, supported by this driver, have two sets of registers:
* (main) interrupt registers control peripheral interrupt sources;
* device interrupt registers configure per-device (network interface)
interrupts and act as an extra stage before the main interrupt registers.

In the driver unmask code, device trigger registers are used in the mask
calculation of the main interrupt sticky register, mixing two kinds of
registers.
This mix up does not manifest itself because the current implementation
only uses level interrupts, but will be evident with addition of the edge
interrupts. The first patch fixes this mix up.

Second patch adds the comment to the sticky bit clearing code as it's not
immediately obvious why Serval family is not handled specially, even though
it has only one interrupt trigger register replication.

Interrupt controller behavior was tested on Jaguar2C VSC7448.

Sergey Matsievskiy (2):
  irqchip/ocelot: Fix trigger register address
  irqchip/ocelot: Comment sticky register clearing code

 drivers/irqchip/irq-mscc-ocelot.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

-- 
2.39.2