linux-kernel - [PATCH 2/2] irqchip/ocelot: Comment sticky register clearing code

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Message-Id: <20240925184416.54204-3-matsievskiysv@gmail.com>
Date: Wed, 25 Sep 2024 21:44:16 +0300
From: Sergey Matsievskiy <matsievskiysv@...il.com>
To: tglx@...utronix.de
Cc: maz@...nel.org,
	alexandre.belloni@...tlin.com,
	gregory.clement@...tlin.com,
	lars.povlsen@...rochip.com,
	UNGLinuxDriver@...rochip.com,
	linux-mips@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Sergey Matsievskiy <matsievskiysv@...il.com>
Subject: [PATCH 2/2] irqchip/ocelot: Comment sticky register clearing code

Add comment to the sticky register clearing code.

Signed-off-by: Sergey Matsievskiy <matsievskiysv@...il.com>
---
 drivers/irqchip/irq-mscc-ocelot.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index c19ab379e8c5..3dc745b14caf 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -84,6 +84,12 @@ static void ocelot_irq_unmask(struct irq_data *data)
 	u32 val;
 
 	irq_gc_lock(gc);
+	/*
+	 * Clear sticky bits for edge mode interrupts.
+	 * Serval has only one trigger register replication, but the adjacent
+	 * register is always read as zero, so there's no need to handle this
+	 * case separately.
+	 */
 	val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
 		irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
 	if (!(val & mask))
-- 
2.39.2