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Message-Id: <172722553796.384629.2084285836291139720.b4-ty@codeconstruct.com.au>
Date: Wed, 25 Sep 2024 10:22:17 +0930
From: Andrew Jeffery <andrew@...econstruct.com.au>
To: patrick@...cx.xyz, Delphine CC Chiu <Delphine_CC_Chiu@...ynn.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Joel Stanley <joel@....id.au>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 0/2] Adjust the setting for SPI flash of yosemite4
On Tue, 24 Sep 2024 17:44:28 +0800, Delphine CC Chiu wrote:
> - v2
> - Split the patches for different targets.
> - v1
> - Revise SPI flash to dual mode.
> - Revise flash layout to 128MB.
>
> Ricky CX Wu (2):
> ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode
> ARM: dts: aspeed: yosemite4: revise flash layout to 128MB
>
> [...]
Thanks, I've applied this to be picked up through the BMC tree.
--
Andrew Jeffery <andrew@...econstruct.com.au>
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