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Message-ID: <20240925113641.1297102-220-sashal@kernel.org>
Date: Wed, 25 Sep 2024 07:27:21 -0400
From: Sasha Levin <sashal@...nel.org>
To: linux-kernel@...r.kernel.org,
	stable@...r.kernel.org
Cc: "Ahmed, Muhammad" <Ahmed.Ahmed@....com>,
	Charlene Liu <charlene.liu@....com>, Ahmed@....codeaurora.org,
	Zaeem Mohamed <zaeem.mohamed@....com>,
	Daniel Wheeler <daniel.wheeler@....com>,
	Alex Deucher <alexander.deucher@....com>,
	Sasha Levin <sashal@...nel.org>, harry.wentland@....com,
	sunpeng.li@....com, Rodrigo.Siqueira@....com,
	christian.koenig@....com, Xinhui.Pan@....com, airlied@...il.com,
	daniel@...ll.ch, daniel.miess@....com, wayne.lin@....com,
	nicholas.kazlauskas@....com, yi-lchen@....com, alex.hung@....com,
	ilya.bakoulin@....com, harikrishna.revalla@....com,
	amd-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org
Subject: [PATCH AUTOSEL 6.11 220/244] drm/amd/display: guard write a 0 post_divider value to HW

From: "Ahmed, Muhammad" <Ahmed.Ahmed@....com>

[ Upstream commit 5d666496c24129edeb2bcb500498b87cc64e7f07 ]

[why]
post_divider_value should not be 0.

Reviewed-by: Charlene Liu <charlene.liu@....com>
Signed-off-by: Ahmed, Muhammad <Ahmed.Ahmed@....com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@....com>
Tested-by: Daniel Wheeler <daniel.wheeler@....com>
Signed-off-by: Alex Deucher <alexander.deucher@....com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
 drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 68cd3258f4a97..a64d8f3ec93a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -47,7 +47,8 @@ static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg)
 	uint32_t dispclk_rdivider_value = 0;
 
 	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value);
-	REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);
+	if (dispclk_rdivider_value != 0)
+		REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);
 }
 
 static void dcn35_set_dppclk_enable(struct dccg *dccg,
-- 
2.43.0


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