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Message-ID: <b3842173-7074-4bcb-80f4-1f6f8cb38a52@collabora.com>
Date: Thu, 26 Sep 2024 10:33:36 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Fei Shao <fshao@...omium.org>
Cc: Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>, Rob Herring <robh@...nel.org>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH 5/6] arm64: dts: mediatek: mt8188: Move vdec1 power domain
under vdec0
Il 25/09/24 12:57, Fei Shao ha scritto:
> There are two hardware IP blocks in MT8188 video decoder pipeline:
> vdec-lat and vdec-core, which are powered by vdec0 and vdec1 power
> domains respectively.
>
> We noticed that vdec-core needs to be powered down before vdec-lat
> during suspend to prevent failures. It's unclear if it's an intended
> hardware design or due to power isolation glitch. But in any case, we
> observed a power-off sequence here, and it can be considered as an
> indirect dependency implication between the vdec0 and vdec1 domains.
>
> Given that, update vdec1 as a sub-domain of vdec0 to enforce the
> sequence. Also, use more specific clock names for both power domains.
>
As far as I know, yes, there is a sequence:
- Cores (mtk-vcodec-core) gets suspended first
- Then the LATs gets suspended (mtk-vcodec-lat)
- Finally, the LAT SoC gets suspended (mtk-vcodec-lat-soc)
...but you checked that downstream, and your downstream misses the lat-soc HW
instance, and only has the lat one.
Are you sure that this is not the reason why you're getting this issue? :-)
Otherwise, I feel like we must ask for some clarification from MediaTek, as
I'm mostly sure that the two cores are independent from each other (but I
might, of course, be wrong!).
Cheers,
Angelo
> Signed-off-by: Fei Shao <fshao@...omium.org>
> ---
>
> arch/arm64/boot/dts/mediatek/mt8188.dtsi | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index ff5c8e0597f9..a6cd08ea74eb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -1064,20 +1064,22 @@ power-domain@...188_POWER_DOMAIN_VPPSYS1 {
> #power-domain-cells = <0>;
> };
>
> - power-domain@...188_POWER_DOMAIN_VDEC1 {
> - reg = <MT8188_POWER_DOMAIN_VDEC1>;
> - clocks = <&vdecsys CLK_VDEC2_LARB1>;
> - clock-names = "ss-vdec";
> - mediatek,infracfg = <&infracfg_ao>;
> - #power-domain-cells = <0>;
> - };
> -
> power-domain@...188_POWER_DOMAIN_VDEC0 {
> reg = <MT8188_POWER_DOMAIN_VDEC0>;
> clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
> - clock-names = "ss-vdec";
> + clock-names = "ss-vdec1-soc-l1";
> mediatek,infracfg = <&infracfg_ao>;
> - #power-domain-cells = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + power-domain@...188_POWER_DOMAIN_VDEC1 {
> + reg = <MT8188_POWER_DOMAIN_VDEC1>;
> + clocks = <&vdecsys CLK_VDEC2_LARB1>;
> + clock-names = "ss-vdec2-l1";
> + mediatek,infracfg = <&infracfg_ao>;
> + #power-domain-cells = <0>;
> + };
> };
>
> cam_vcore: power-domain@...188_POWER_DOMAIN_CAM_VCORE {
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