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Message-Id: <20240926144513.71349-3-v.pavani@samsung.com>
Date: Thu, 26 Sep 2024 20:15:13 +0530
From: Varada Pavani <v.pavani@...sung.com>
To: krzk@...nel.org, aswani.reddy@...sung.com, pankaj.dubey@...sung.com,
s.nawrocki@...sung.com, cw00.choi@...sung.com, alim.akhtar@...sung.com,
mturquette@...libre.com, sboyd@...nel.org,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: gost.dev@...sung.com, Varada Pavani <v.pavani@...sung.com>,
stable@...r.kernel.org
Subject: [PATCH 2/2] clk: samsung: Fixes PLL locktime for PLL142XX used on
FSD platfom
Add PLL locktime for PLL142XX controller.
Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
Cc: stable@...r.kernel.org
Signed-off-by: Varada Pavani <v.pavani@...sung.com>
---
drivers/clk/samsung/clk-pll.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 4be879ab917e..d4c5ae20de4f 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
*/
/* Maximum lock time can be 270 * PDIV cycles */
#define PLL35XX_LOCK_FACTOR (270)
+#define PLL142XX_LOCK_FACTOR (150)
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
@@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
}
/* Set PLL lock time. */
- writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
+ if (pll->type == pll_142xx)
+ writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
+ pll->lock_reg);
+ else
+ writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
pll->lock_reg);
/* Change PLL PMS values */
--
2.17.1
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