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Message-ID: <CAF6AEGtgSCpsOvikwEchyLhT3mnA38oanLGgbBvJVPhaFa+M2g@mail.gmail.com>
Date: Fri, 27 Sep 2024 09:13:45 -0700
From: Rob Clark <robdclark@...il.com>
To: Antonino Maniscalco <antomani103@...il.com>
Cc: Sean Paul <sean@...rly.run>, Konrad Dybcio <konrad.dybcio@...aro.org>,
Abhinav Kumar <quic_abhinavk@...cinc.com>, Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Marijn Suijten <marijn.suijten@...ainline.org>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
Jonathan Corbet <corbet@....net>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
Akhil P Oommen <quic_akhilpo@...cinc.com>, Neil Armstrong <neil.armstrong@...aro.org>,
Sharat Masetty <smasetty@...eaurora.org>
Subject: Re: [PATCH v6 05/11] drm/msm/a6xx: Implement preemption for a7xx targets
On Thu, Sep 26, 2024 at 2:17 PM Antonino Maniscalco
<antomani103@...il.com> wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from coarse grained(ringbuffer level) to a more fine grained
> such as draw-call level or a bin boundary level preemption. This patch
> enables the basic preemption level, with more fine grained preemption
> support to follow.
>
> Reviewed-by: Akhil P Oommen <quic_akhilpo@...cinc.com>
> Tested-by: Neil Armstrong <neil.armstrong@...aro.org> # on SM8650-QRD
> Tested-by: Neil Armstrong <neil.armstrong@...aro.org> # on SM8550-QRD
> Tested-by: Neil Armstrong <neil.armstrong@...aro.org> # on SM8450-HDK
> Signed-off-by: Sharat Masetty <smasetty@...eaurora.org>
> Signed-off-by: Antonino Maniscalco <antomani103@...il.com>
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 283 +++++++++++++++++++++-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 168 +++++++++++++
> drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 377 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_ringbuffer.h | 7 +
> 5 files changed, 825 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index f5e2838c6a76505b353f83c9fe9c997f1c282701..32e915109a59dda96ed76ddd2b4f57bb225f4572 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -23,6 +23,7 @@ adreno-y := \
> adreno/a6xx_gpu.o \
> adreno/a6xx_gmu.o \
> adreno/a6xx_hfi.o \
> + adreno/a6xx_preempt.o \
>
> adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 6e065500b64d6d95599d89c33e6703c92f210047..355a3e210335d60a5bed0ee287912271c353402a 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -16,6 +16,84 @@
>
> #define GPU_PAS_ID 13
>
> +/* IFPC & Preemption static powerup restore list */
> +static const uint32_t a7xx_pwrup_reglist[] = {
> + REG_A6XX_UCHE_TRAP_BASE,
> + REG_A6XX_UCHE_TRAP_BASE + 1,
> + REG_A6XX_UCHE_WRITE_THRU_BASE,
> + REG_A6XX_UCHE_WRITE_THRU_BASE + 1,
> + REG_A6XX_UCHE_GMEM_RANGE_MIN,
> + REG_A6XX_UCHE_GMEM_RANGE_MIN + 1,
> + REG_A6XX_UCHE_GMEM_RANGE_MAX,
> + REG_A6XX_UCHE_GMEM_RANGE_MAX + 1,
> + REG_A6XX_UCHE_CACHE_WAYS,
> + REG_A6XX_UCHE_MODE_CNTL,
> + REG_A6XX_RB_NC_MODE_CNTL,
> + REG_A6XX_RB_CMP_DBG_ECO_CNTL,
> + REG_A7XX_GRAS_NC_MODE_CNTL,
> + REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,
> + REG_A6XX_UCHE_GBIF_GX_CONFIG,
> + REG_A6XX_UCHE_CLIENT_PF,
> + REG_A6XX_TPL1_DBG_ECO_CNTL1,
> +};
> +
> +static const uint32_t a7xx_ifpc_pwrup_reglist[] = {
> + REG_A6XX_TPL1_NC_MODE_CNTL,
> + REG_A6XX_SP_NC_MODE_CNTL,
> + REG_A6XX_CP_DBG_ECO_CNTL,
> + REG_A6XX_CP_PROTECT_CNTL,
> + REG_A6XX_CP_PROTECT(0),
> + REG_A6XX_CP_PROTECT(1),
> + REG_A6XX_CP_PROTECT(2),
> + REG_A6XX_CP_PROTECT(3),
> + REG_A6XX_CP_PROTECT(4),
> + REG_A6XX_CP_PROTECT(5),
> + REG_A6XX_CP_PROTECT(6),
> + REG_A6XX_CP_PROTECT(7),
> + REG_A6XX_CP_PROTECT(8),
> + REG_A6XX_CP_PROTECT(9),
> + REG_A6XX_CP_PROTECT(10),
> + REG_A6XX_CP_PROTECT(11),
> + REG_A6XX_CP_PROTECT(12),
> + REG_A6XX_CP_PROTECT(13),
> + REG_A6XX_CP_PROTECT(14),
> + REG_A6XX_CP_PROTECT(15),
> + REG_A6XX_CP_PROTECT(16),
> + REG_A6XX_CP_PROTECT(17),
> + REG_A6XX_CP_PROTECT(18),
> + REG_A6XX_CP_PROTECT(19),
> + REG_A6XX_CP_PROTECT(20),
> + REG_A6XX_CP_PROTECT(21),
> + REG_A6XX_CP_PROTECT(22),
> + REG_A6XX_CP_PROTECT(23),
> + REG_A6XX_CP_PROTECT(24),
> + REG_A6XX_CP_PROTECT(25),
> + REG_A6XX_CP_PROTECT(26),
> + REG_A6XX_CP_PROTECT(27),
> + REG_A6XX_CP_PROTECT(28),
> + REG_A6XX_CP_PROTECT(29),
> + REG_A6XX_CP_PROTECT(30),
> + REG_A6XX_CP_PROTECT(31),
> + REG_A6XX_CP_PROTECT(32),
> + REG_A6XX_CP_PROTECT(33),
> + REG_A6XX_CP_PROTECT(34),
> + REG_A6XX_CP_PROTECT(35),
> + REG_A6XX_CP_PROTECT(36),
> + REG_A6XX_CP_PROTECT(37),
> + REG_A6XX_CP_PROTECT(38),
> + REG_A6XX_CP_PROTECT(39),
> + REG_A6XX_CP_PROTECT(40),
> + REG_A6XX_CP_PROTECT(41),
> + REG_A6XX_CP_PROTECT(42),
> + REG_A6XX_CP_PROTECT(43),
> + REG_A6XX_CP_PROTECT(44),
> + REG_A6XX_CP_PROTECT(45),
> + REG_A6XX_CP_PROTECT(46),
> + REG_A6XX_CP_PROTECT(47),
> + REG_A6XX_CP_AHB_CNTL,
> +};
Should we put these in a6xx_catalog.c, in a6xx_info instead? I guess
they'd differ on a6xx if we enabled preemption there (at a minimum,
the # of CP_PROTECT regs differs btwn a6xx sub-generations)
BR,
-R
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