linux-kernel - Re: [PATCH] dt-bindings: spi: xilinx: Add clocks & clock-names properties

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Message-ID: <20240928-postcard-lively-c0c9bbe74d04@spud>
Date: Sat, 28 Sep 2024 21:12:18 +0100
From: Conor Dooley <conor@...nel.org>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@....com>,
	"broonie@...nel.org" <broonie@...nel.org>,
	"robh@...nel.org" <robh@...nel.org>,
	"krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>,
	"Simek, Michal" <michal.simek@....com>,
	"linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"git (AMD-Xilinx)" <git@....com>,
	"amitrkcian2002@...il.com" <amitrkcian2002@...il.com>
Subject: Re: [PATCH] dt-bindings: spi: xilinx: Add clocks & clock-names
 properties

On Sat, Sep 28, 2024 at 10:19:01AM +0200, Krzysztof Kozlowski wrote:
> On 27/09/2024 11:30, Mahapatra, Amit Kumar wrote:
> > Hello Conor,
> > 
> > 
> >>>> Subject: Re: [PATCH] dt-bindings: spi: xilinx: Add clocks &
> >>>> clock-names properties
> >>>>
> >>>> On Mon, Sep 23, 2024 at 06:02:42PM +0530, Amit Kumar Mahapatra wrote:
> >>>>> Include the 'clocks' and 'clock-names' properties in the AXI
> >>>>> Quad-SPI bindings. When the AXI4-Lite interface is enabled, the
> >>>>> core operates in legacy mode, maintaining backward compatibility
> >>>>> with version 1.00, and uses 's_axi_aclk' and 'ext_spi_clk'. For
> >>>>> the AXI interface, it uses 's_axi4_aclk' and 'ext_spi_clk'.

> >>>>> +      properties:
> >>>>> +        clock-names:
> >>>>> +          items:
> >>>>> +            - const: s_axi_aclk
> >>>>> +            - const: ext_spi_clk
> >>>>
> >>>> These are all clocks, there should be no need to have "clk" in the names.
> >>>
> >>> These are the names exported by the IP and used by the DTG.
> >>
> >> So? This is a binding, not a verilog file.
> > 
> > Axi Quad SPI is an FPGA-based IP, and the clock names are derived from the 
> > IP signal names as specified in the IP documentation [1]. 
> > We chose these names to ensure alignment with the I/O signal names listed 
> > in Table 2-2 on page 19 of [1].
> > 
> > [1] chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/https://www.amd.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf
> 
> So if hardware engineers call them "pink_pony_clk_aclk_really_clk" we
> should follow...
> 
>  - bus or axi
>  - ext_spi or spi
> 
> You have descriptions of each item to reference real signals. Conor's
> comment is valid - do no make it verilog file.
> 
> > 
> >>
> >>>>> +
> >>>>> +    else:
> >>>>> +      properties:
> >>>>> +        clock-names:
> >>>>> +          items:
> >>>>> +            - const: s_axi4_aclk
> >>>>> +            - const: ext_spi_clk
> 
> Nah, these are the same.

They may be different, depending on whether or not the driver has to
handle "axi4-lite" versus "axi" differently. That said, I find the
commit message kinda odd in that it states that axi4-lite goes with
the s_axi_aclk clock and axi goes with s_axi4_aclk. Seems backwards..

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