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Message-ID: <20240929113848.6d3affb2@jic23-huawei>
Date: Sun, 29 Sep 2024 11:38:48 +0100
From: Jonathan Cameron <jic23@...nel.org>
To: Nuno Sá <noname.nuno@...il.com>
Cc: Angelo Dureghello <adureghello@...libre.com>, Lars-Peter Clausen
<lars@...afoo.de>, Michael Hennerich <Michael.Hennerich@...log.com>, Nuno
Sa <nuno.sa@...log.com>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Olivier Moysan
<olivier.moysan@...s.st.com>, linux-iio@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
dlechner@...libre.com
Subject: Re: [PATCH v3 01/10] iio: backend: adi-axi-dac: fix wrong register
bitfield
On Fri, 20 Sep 2024 14:45:42 +0200
Nuno Sá <noname.nuno@...il.com> wrote:
> On Thu, 2024-09-19 at 11:19 +0200, Angelo Dureghello wrote:
> > From: Angelo Dureghello <adureghello@...libre.com>
> >
> > Fix ADI_DAC_R1_MODE of AXI_DAC_REG_CNTRL_2.
> >
> > Both generic DAC and ad3552r DAC IPs docs are reporting
> > bit 5 for it.
> >
> > https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
> > https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html
Can also turn these into Link: tags though that isn't particularly
important for reference links like these. If you do, they are
part of the main tags block so no blank line between them
and your SoB.
> >
> > Signed-off-by: Angelo Dureghello <adureghello@...libre.com>
> > ---
>
> Ouch... Missing Fixes tag. With that,
>
> Reviewed-by: Nuno Sa <nuno.sa@...log.com>
>
> > drivers/iio/dac/adi-axi-dac.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c
> > index 0cb00f3bec04..b8b4171b8043 100644
> > --- a/drivers/iio/dac/adi-axi-dac.c
> > +++ b/drivers/iio/dac/adi-axi-dac.c
> > @@ -46,7 +46,7 @@
> > #define AXI_DAC_REG_CNTRL_1 0x0044
> > #define AXI_DAC_SYNC BIT(0)
> > #define AXI_DAC_REG_CNTRL_2 0x0048
> > -#define ADI_DAC_R1_MODE BIT(4)
> > +#define ADI_DAC_R1_MODE BIT(5)
> > #define AXI_DAC_DRP_STATUS 0x0074
> > #define AXI_DAC_DRP_LOCKED BIT(17)
> > /* DAC Channel controls */
> >
>
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