linux-kernel - Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings

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Message-ID: <cldodjlatbxjrsjhympium57k2ta35hzets35xfv57gedkqdcg@77dzf7ro5hm5>
Date: Sun, 29 Sep 2024 21:49:17 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Ian Dannapel <iansdannapel@...il.com>
Cc: mdf@...nel.org, hao.wu@...el.com, yilun.xu@...el.com, trix@...hat.com, 
	robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	neil.armstrong@...aro.org, heiko.stuebner@...rry.de, rafal@...ecki.pl, 
	linus.walleij@...aro.org, linux-fpga@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] dt-bindings: fpga: Add Efinix serial SPI programming
 bindings

On Sat, Sep 28, 2024 at 04:26:03PM +0200, Ian Dannapel wrote:
> Am Sa., 28. Sept. 2024 um 14:53 Uhr schrieb Krzysztof Kozlowski
> <krzk@...nel.org>:
> >
> > On 28/09/2024 14:33, Ian Dannapel wrote:
> > >>>>
> > >>>>> +
> > >>>>> +  spi-cpha: true
> > >>>>> +
> > >>>>> +  spi-cpol: true
> > >>>>> +
> > >>>>> +  spi-max-frequency:
> > >>>>> +    maximum: 25000000
> > >>>>> +
> > >>>>> +  reg:
> > >>>>> +    maxItems: 1
> > >>>>> +
> > >>>>> +  creset-gpios:
> > >>>>
> > >>>> reset-gpios
> > >>>>
> > >>>> Do not invent own properties.
> > >>>>
> > >>>>> +    description:
> > >>>>> +      reset and re-configuration trigger pin (low active)
> > >>>>> +    maxItems: 1
> > >>>>> +
> > >>>>> +  cs-gpios:
> > >>>>> +    description:
> > >>>>> +      chip-select pin (low active)
> > >>>>
> > >>>> Eee? That's a property of controller, not child. Aren't you duplicating
> > >>>> existing controller property?
> > >>> This device uses this pin in combination with the reset to enter the
> > >>> programming mode. Also, the driver must guarantee that the pin is
> > >>
> > >> Isn't this the same on every SPI device?
> > > Yes, but I was not very clear. In this case the pin must be hold
> > > active including entering the programming mode. And if the controller
> >
> > Just like every CS, no?
> >
> > The only difference is that you must send entire programming sequence
> > without releasing the CS.
> >
> > > transfers the data in bursts, the pin is also not allowed to go
> > > inactive between transfer bursts.
> > >>
> > >>> active for the whole transfer process, including ending dummy bits.
> > >>> This is why I added a warning to NOT use this driver with other
> > >>> devices on the same bus.
> > >>
> > >> Not really related. None of this grants exception from duplicating
> > >> controller's property.
> > >>
> > >> How do you think it will even work in Linux, if same GPIO is requested
> > >> twice (imagine controller also has it)? Till now, this would be -EBUSY.
> > > I expected that the controller is not able request the same gpio. From
> > > the controller point of view, it is a device that does not have a chip
> > > select. Not sure if the controller would be able to get to this gpio
> > > if it is not explicitly given.
> >
> > But it could be given. Don't think only about your case.
> it won't work if the controller also may request this gpio or interfere with it.

Then your binding is incomplete, I would say. What stops anyone from
providing the same GPIO for CS in controller node, like typical bindings
expect?

> >
> > Your description earlier clearly suggests it is CS. Description here
> > suggests it is not a CS.
> >
> > No clue then.
> >
> > >>
> > >> But regardless of implementation, I still do not understand why do you
> > >> need duplicate same chip-select. Maybe just the naming is the confusion,
> > >> dunno.
> > > This could be an option to make the difference to a "real chip-select"
> > > clear, but it would drift away from the datasheet naming. Eg,
> > > prog-select?
> >
> > Please go back to datasheet. Which pin is this? CS, yes or not? If not,
> > then which other pin is CS?
> Yes, this pin in question is referred to as the Chip Select (CS) or
> Slave Select in the datasheet and pinout.
> It is used in combination with the reset for entering the programming
> mode and then used for the SPI data transfer to the FPGA’s volatile
> configuration RAM.
> There must be no state change on this CS pin between entering
> programming mode and the completion of the SPI transfer.

You just described CS gpio in parent controller node.

> Since the controller chip-select functionality can't fulfill these
> requirements for this device, the proposed solution is to move this
> pin from the controller to the child driver.

You mix two different things. Where the property should be described and
how it should be handled. child driver is not the matter of bindings.

Best regards,
Krzysztof