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Message-ID: <20240930083854.7267-2-macpaul.lin@mediatek.com>
Date: Mon, 30 Sep 2024 16:38:51 +0800
From: Macpaul Lin <macpaul.lin@...iatek.com>
To: Chun-Kuang Hu <chunkuang.hu@...nel.org>, Philipp Zabel
<p.zabel@...gutronix.de>, David Airlie <airlied@...il.com>, Simona Vetter
<simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Yong Wu <yong.wu@...iatek.com>, "Joerg
Roedel" <joro@...tes.org>, Will Deacon <will@...nel.org>, Robin Murphy
<robin.murphy@....com>, Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>, "Rohit
Agarwal" <rohiagar@...omium.org>, <dri-devel@...ts.freedesktop.org>,
<linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev>,
<linux-arm-kernel@...ts.infradead.org>, Alexandre Mergnat
<amergnat@...libre.com>
CC: Bear Wang <bear.wang@...iatek.com>, Pablo Sun <pablo.sun@...iatek.com>,
Macpaul Lin <macpaul.lin@...iatek.com>, Macpaul Lin <macpaul@...il.com>, "Sen
Chu" <sen.chu@...iatek.com>, Chris-qj chen <chris-qj.chen@...iatek.com>,
MediaTek Chromebook Upstream
<Project_Global_Chrome_Upstream_Group@...iatek.com>, Chen-Yu Tsai
<wenst@...omium.org>
Subject: [PATCH v4 2/5] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs
The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due
to an excessively long 'interrupts' property. The error message was:
infra-iommu@...15000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0],
[0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]]
is too long
To address this issue, update the compatbile matching rule for
'interrupts' property. This change allows flexibility in the number
of interrupts for new SoCs like MT8195.
The purpose of these 5 interrupts is also added into description.
Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema")
Signed-off-by: Macpaul Lin <macpaul.lin@...iatek.com>
---
.../bindings/iommu/mediatek,iommu.yaml | 28 ++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
Changes for v2:
- commit message: re-formatting and add a description of adding 5 interrupts.
- add 'description' and 'maxItems: 5' for 'interrupt' property of
'mt8195-iommu-infra'
- others keeps 'maxItems: 1'
Changes for v3:
- Refine the description for 'interrupts' property and fixes the compatible
matching rules.
- Refine commit message.
Changes for v4:
- add missing 'minItems: 5' to 'mediatek,mt8195-iommu-infra'.
Thanks the explanation from Conor and Krzysztof.
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index ea6b0f5f24de..33b330d83e01 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -96,7 +96,15 @@ properties:
maxItems: 1
interrupts:
- maxItems: 1
+ description: |
+ Usually, the IOMMU requires only 1 interrupt.
+
+ The IOMMU of MT8195 has 5 banks: 0/1/2/3/4.
+ Each bank has a set of APB registers corresponding to the
+ normal world, protected world 1/2/3, and secure world, respectively.
+ Therefore, 5 interrupt numbers are needed for MT8195.
+ minItems: 1
+ maxItems: 5
clocks:
items:
@@ -210,6 +218,24 @@ allOf:
required:
- mediatek,larbs
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8195-iommu-infra
+
+ then:
+ properties:
+ interrupts:
+ minItems: 5
+ maxItems: 5
+
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
additionalProperties: false
examples:
--
2.45.2
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