| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20241001024356.1096072-22-anshuman.khandual@arm.com> Date: Tue, 1 Oct 2024 08:13:30 +0530 From: Anshuman Khandual <anshuman.khandual@....com> To: linux-kernel@...r.kernel.org, kvmarm@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org, maz@...nel.org Cc: Anshuman Khandual <anshuman.khandual@....com>, Oliver Upton <oliver.upton@...ux.dev>, James Morse <james.morse@....com>, Suzuki K Poulose <suzuki.poulose@....com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org> Subject: [PATCH 21/47] arm64/sysreg: Add register fields for SPMSCR_EL1 This adds register fields for SPMSCR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas <catalin.marinas@....com> Cc: Will Deacon <will@...nel.org> Cc: Mark Brown <broonie@...nel.org> Cc: linux-arm-kernel@...ts.infradead.org Cc: linux-kernel@...r.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@....com> --- arch/arm64/tools/sysreg | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 55836abbc8cc..44fabd1f3aef 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -130,6 +130,15 @@ Sysreg PMCCNTSVR_EL1 2 0 14 11 7 Field 63:0 CCNT EndSysreg +Sysreg SPMSCR_EL1 2 7 9 14 7 +Field 63:32 IMP_DEF +Field 31 RAO +Res0 30:5 +Field 4 NAO +Res0 3:1 +Field 0 SO +EndSysreg + Sysreg ID_PFR0_EL1 3 0 0 1 0 Res0 63:32 UnsignedEnum 31:28 RAS -- 2.25.1
Powered by blists - more mailing lists