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Message-ID: <CACRpkdbFD9CiqVwQ5xxZ9SfQtVvDJGCr=8spxBG4u-JQ0PKJ3w@mail.gmail.com>
Date: Tue, 1 Oct 2024 16:18:04 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Billy Tsai <billy_tsai@...eedtech.com>
Cc: brgl@...ev.pl, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
joel@....id.au, andrew@...econstruct.com.au, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org,
BMC-SW@...eedtech.com, Peter.Yin@...ntatw.com, Jay_Zhang@...ynn.com
Subject: Re: [PATCH v4 6/6] gpio: aspeed: Add the flush write to ensure the
write complete.
On Thu, Sep 19, 2024 at 11:43 AM Billy Tsai <billy_tsai@...eedtech.com> wrote:
> Performing a dummy read ensures that the register write operation is fully
> completed, mitigating any potential bus delays that could otherwise impact
> the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to
> control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application
> sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on
> a delay function to ensure the clock frequency does not exceed 1 MHz.
> However, this can lead to rapid toggling of the GPIO because the write
> operation is POSTed and does not wait for a bus acknowledgment.
>
> Signed-off-by: Billy Tsai <billy_tsai@...eedtech.com>
If this applies cleanly on mainline I think it should go into fixes as-is.
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>
Yours,
Linus Walleij
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