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Message-Id: <20241001024356.1096072-37-anshuman.khandual@arm.com> Date: Tue, 1 Oct 2024 08:13:45 +0530 From: Anshuman Khandual <anshuman.khandual@....com> To: linux-kernel@...r.kernel.org, kvmarm@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org, maz@...nel.org Cc: Anshuman Khandual <anshuman.khandual@....com>, Oliver Upton <oliver.upton@...ux.dev>, James Morse <james.morse@....com>, Suzuki K Poulose <suzuki.poulose@....com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, Mark Brown <broonie@...nel.org> Subject: [PATCH 36/47] arm64/sysreg: Add register fields for SPMCFGR_EL1 This adds register fields for SPMCFGR_EL1 as per the definitions based on DDI0601 2024-06. Cc: Catalin Marinas <catalin.marinas@....com> Cc: Will Deacon <will@...nel.org> Cc: Mark Brown <broonie@...nel.org> Cc: linux-arm-kernel@...ts.infradead.org Cc: linux-kernel@...r.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@....com> --- arch/arm64/tools/sysreg | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 270058558a24..a07d89e43498 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -180,6 +180,24 @@ Field 15:8 Aff1 Field 7:0 Aff0 EndSysreg +Sysreg SPMCFGR_EL1 2 0 9 13 7 +Res0 63:32 +Field 31:28 NCG +Res0 27:25 +Field 24 HDBG +Field 23 TR0 +Field 22 SS +Field 21 FZ0 +Field 20 MSI +Field 19 RAO +Res0 18 +Field 17 NA +Field 16 EX +Field 15:14 RAZ +Field 13:8 SIZE +Field 7:0 N +EndSysreg + Sysreg SPMINTENSET_EL1 2 0 9 14 1 Field 63 P63 Field 62 P62 -- 2.25.1
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