linux-kernel - [PATCH RFC 1/7] x86/microcode/intel: Remove unnecessary cache writeback and invalidation

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Message-Id: <20241001161042.465584-2-chang.seok.bae@intel.com>
Date: Tue,  1 Oct 2024 09:10:36 -0700
From: "Chang S. Bae" <chang.seok.bae@...el.com>
To: linux-kernel@...r.kernel.org
Cc: x86@...nel.org,
	tglx@...utronix.de,
	mingo@...hat.com,
	bp@...en8.de,
	dave.hansen@...ux.intel.com,
	chang.seok.bae@...el.com,
	Yan Hua Wu <yanhua1.wu@...el.com>,
	William Xie <william.xie@...el.com>,
	Ashok Raj <ashok.raj@...el.com>
Subject: [PATCH RFC 1/7] x86/microcode/intel: Remove unnecessary cache writeback and invalidation

Currently, an unconditional cache flush is performed during every
microcode update. Although the original changelog did not mention a
specific erratum, this measure was primarily intended to address a
specific microcode bug, the load of which has already been blocked by
is_blacklisted(). Therefore, this cache flush is no longer necessary.

Additionally, the side effects of doing this have been overlooked. It
increases CPU rendezvous time during late loading, where the cache flush
takes between 1x to 3.5x longer than the actual microcode update.

Remove native_wbinvd() and update the erratum name to align with the
latest errata documentation:

    https://cdrdv2.intel.com/v1/dl/getContent/334165
    # Document 334163 Version 022US

Fixes: 91df9fdf5149 ("x86/microcode/intel: Writeback and invalidate caches before updating microcode")
Reported-by: Yan Hua Wu <yanhua1.wu@...el.com>
Reported-by: William Xie <william.xie@...el.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@...el.com>
Tested-by: Yan Hua Wu <yanhua1.wu@...el.com>
Acked-by: Ashok Raj <ashok.raj@...el.com>
---
The original patch [1] was posted earlier, with a cover letter [2]
providing context on the prior investigation into the cache flush.

Changes in this revision include:
* Added Ashok's acknowledgment tag
* Corrected the subject prefix
* Included the link to the errata documentation in the changelog
* Refined the changelog

This fix is particularly relevant to staging, as the cache flush was
found to significantly increase latency during staged late loading.

[1]: https://lore.kernel.org/all/20240701212012.21499-2-chang.seok.bae@intel.com/
[2]: https://lore.kernel.org/all/20240701212012.21499-1-chang.seok.bae@intel.com/
---
 arch/x86/kernel/cpu/microcode/intel.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 815fa67356a2..f3d534807d91 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -319,12 +319,6 @@ static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci,
 		return UCODE_OK;
 	}
 
-	/*
-	 * Writeback and invalidate caches before updating microcode to avoid
-	 * internal issues depending on what the microcode is updating.
-	 */
-	native_wbinvd();
-
 	/* write microcode via MSR 0x79 */
 	native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 
@@ -574,14 +568,14 @@ static bool is_blacklisted(unsigned int cpu)
 	/*
 	 * Late loading on model 79 with microcode revision less than 0x0b000021
 	 * and LLC size per core bigger than 2.5MB may result in a system hang.
-	 * This behavior is documented in item BDF90, #334165 (Intel Xeon
+	 * This behavior is documented in item BDX90, #334165 (Intel Xeon
 	 * Processor E7-8800/4800 v4 Product Family).
 	 */
 	if (c->x86_vfm == INTEL_BROADWELL_X &&
 	    c->x86_stepping == 0x01 &&
 	    llc_size_per_core > 2621440 &&
 	    c->microcode < 0x0b000021) {
-		pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
+		pr_err_once("Erratum BDX90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
 		pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
 		return true;
 	}
-- 
2.43.0