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Message-ID: <20241001210446.14547-1-mattc@purestorage.com>
Date: Tue,  1 Oct 2024 15:04:46 -0600
From: Matthew W Carlis <mattc@...estorage.com>
To: macro@...am.me.uk
Cc: alex.williamson@...hat.com,
	bhelgaas@...gle.com,
	davem@...emloft.net,
	david.abdurachmanov@...il.com,
	edumazet@...gle.com,
	helgaas@...nel.org,
	kuba@...nel.org,
	leon@...nel.org,
	linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org,
	linux-rdma@...r.kernel.org,
	linuxppc-dev@...ts.ozlabs.org,
	lukas@...ner.de,
	mahesh@...ux.ibm.com,
	mattc@...estorage.com,
	mika.westerberg@...ux.intel.com,
	netdev@...r.kernel.org,
	npiggin@...il.com,
	oohall@...il.com,
	pabeni@...hat.com,
	pali@...nel.org,
	saeedm@...dia.com,
	sr@...x.de,
	wilson@...iptree.org
Subject: PCI: Work around PCIe link training failures

I just wanted to follow up with our testing results for the mentioned
patches. It took me a while to get them running in our test pool, but
we just got it going yesterday and the initial results look really good.
We will continue running them in our testing from now on & if any issues
come up I'll try to report them, but otherwise I wanted to say thank you
for entertaining the discussion & reacting so quickly with new patches.

The patches we pulled into our testing:

[PATCH v3 1/4] PCI: Clear the LBMS bit after a link retrain
[PATCH v3 2/4] PCI: Revert to the original speed after PCIe failed link retraining

- Matt

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