linux-kernel - Re: [PATCH v2] phy: ti: phy-j721e-wiz: fix usxgmii configuration

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <59baaefa-4b57-4c76-ad19-3d16eaeb587c@kernel.org>
Date: Tue, 1 Oct 2024 10:51:33 +0300
From: Roger Quadros <rogerq@...nel.org>
To: Siddharth Vadapalli <s-vadapalli@...com>
Cc: vkoul@...nel.org, kishon@...nel.org, thomas.richard@...tlin.com,
 krzysztof.kozlowski@...aro.org, nichen@...as.ac.cn, c-vankar@...com,
 t-patil@...com, linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, srk@...com
Subject: Re: [PATCH v2] phy: ti: phy-j721e-wiz: fix usxgmii configuration



On 01/10/2024 06:10, Siddharth Vadapalli wrote:
> On Mon, Sep 30, 2024 at 05:06:35PM +0300, Roger Quadros wrote:
> 
> Hello Roger,
> 
>> Hi Siddharth,
>>
>> On 30/09/2024 12:57, Siddharth Vadapalli wrote:
>>> Commit b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in
>>> wiz driver") added support for USXGMII mode. In doing so, P0_REFCLK_SEL
>>> was set to "pcs_mac_clk_divx1_ln_0" (0x3) and P0_STANDARD_MODE was set to
>>> LANE_MODE_GEN1, which results in a data rate of 5.15625 Gbps. However,
>>> since the USXGMII mode can support up to 10.3125 Gbps data rate, the
>>> aforementioned fields should be set to "pcs_mac_clk_divx0_ln_0" (0x2) and
>>> LANE_MODE_GEN2 respectively. Fix the configuration accordingly to truly
>>> support USXGMII up to 10G.
>>>
>>> Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver")
>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
> 
> [...]
> 
>>> diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
>>> index a6c0c5607ffd..c6e846d385d2 100644
>>> --- a/drivers/phy/ti/phy-j721e-wiz.c
>>> +++ b/drivers/phy/ti/phy-j721e-wiz.c
>>> @@ -450,8 +450,8 @@ static int wiz_mode_select(struct wiz *wiz)
>>>  		} else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
>>>  			ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
>>>  			ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
>>
>> I'm not sure. Don't we have to change rxfclk as well?
> 
> This patch was validated on a custom board with the J7200 SR 2.0 SoC.
> The signal corresponding to the USXGMII lane of the SERDES was measured
> to be 5 Gbps without this patch and 10 Gbps with this patch applied,
> with no other changes required. Apart from measuring the signal, ping
> was also validated.

Thanks. This is useful piece off information that could go in the commit log.

Reviewed-by: Roger Quadros <rogerq@...nel.org>