linux-kernel - Re: [PATCH 3/3] perf/x86/intel: Support auto counter reload

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Message-ID: <ZvvZ78QAH254TiHe@tassilo>
Date: Tue, 1 Oct 2024 04:16:14 -0700
From: Andi Kleen <ak@...ux.intel.com>
To: kan.liang@...ux.intel.com
Cc: peterz@...radead.org, mingo@...nel.org, acme@...nel.org,
	namhyung@...nel.org, irogers@...gle.com, adrian.hunter@...el.com,
	linux-kernel@...r.kernel.org, eranian@...gle.com,
	thomas.falcon@...el.com
Subject: Re: [PATCH 3/3] perf/x86/intel: Support auto counter reload


I hope the perf tools will support a nicer syntax, the mask is quite
obscure.

On Mon, Sep 30, 2024 at 08:41:22AM -0700, kan.liang@...ux.intel.com wrote:
>  }
>  
> +static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
> +{
> +	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> +	int msr_b, msr_c;
> +
> +	if (!mask && cpuc->acr_cfg_b[idx] == mask)
> +		return;


if (!mask && !cpuc->acr_cfg_b[idx])

> +
> +	if (idx < INTEL_PMC_IDX_FIXED) {
> +		msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;
> +		msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;
> +	} else {
> +		msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;
> +		msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;
> +		idx -= INTEL_PMC_IDX_FIXED;
> +	}

Does this handle metrics correctly?

I assume you ran the fuzzer over this.

> +	if (cpuc->acr_cfg_b[idx] != mask) {
> +		wrmsrl(msr_b + x86_pmu.addr_offset(idx, false), mask);
> +		cpuc->acr_cfg_b[idx] = mask;
> +	}
> +	/* Only need to update the reload value when there is a valid config value. */
> +	if (mask && cpuc->acr_cfg_c[idx] != reload) {
> +		wrmsrl(msr_c + x86_pmu.addr_offset(idx, false), reload);
> +		cpuc->acr_cfg_c[idx] = reload;

Can reload be larger than the counter width? What happens then?

>  	return c2;
>  }
>  
> @@ -3948,6 +4004,78 @@ static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
>  	return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
>  }
>  
> +static bool intel_pmu_is_acr_group(struct perf_event *event)
> +{
> +	if (!hybrid(event->pmu, acr_cntr_mask64))
> +		return false;

Shouldn't this error when the group leader
has the flag set?

> +	/* The group leader has the ACR flag set */
> +	if (is_acr_event_group(event))
> +		return true;
> +
> +	/* The acr_mask is set */
> +	if (event->attr.config2)
> +		return true;

> +		 * the group. Reconfigure the dyn_mask of each X86 event
> +		 * every time when add a new event.
> +		 *
> +		 * Check whether the reloadable counters is enough and
> +		 * initialize the dyn_mask.
> +		 */
> +		if (intel_pmu_acr_check_reloadable_event(event))
> +			return -EINVAL;
> +
> +		/* Reconfigure the dyn_mask for each event */
> +		intel_pmu_set_acr_dyn_mask(leader, event_idx++, event);
> +		for_each_sibling_event(sibling, leader)
> +			intel_pmu_set_acr_dyn_mask(sibling, event_idx++, event);
> +		intel_pmu_set_acr_dyn_mask(event, event_idx, event);
> +

Shouldn't there be an error somewhere when a mask bit is set that
exceeds the group? (maybe I missed it)

I assume it could #GP on the MSR write, or maybe even overflow into
some other field.

-Andi