linux-kernel - Re: [PATCH v10 02/14] dt-bindings: cpus: add a thead vlen register length property

Open Source and information security mailing list archives

Message-ID: <CAFTtA3NwGFioVAeipkA6aCUfRY12jKFJiR7MaCpCYNjdsT7TMQ@mail.gmail.com>
Date: Thu, 3 Oct 2024 00:05:37 +0800
From: Andy Chiu <andybnac@...il.com>
To: Charlie Jenkins <charlie@...osinc.com>
Cc: Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Jisheng Zhang <jszhang@...nel.org>, Chen-Yu Tsai <wens@...e.org>, 
	Jernej Skrabec <jernej.skrabec@...il.com>, Samuel Holland <samuel@...lland.org>, 
	Samuel Holland <samuel.holland@...ive.com>, Jonathan Corbet <corbet@....net>, 
	Shuah Khan <shuah@...nel.org>, Guo Ren <guoren@...nel.org>, Evan Green <evan@...osinc.com>, 
	Andy Chiu <andy.chiu@...ive.com>, Jessica Clarke <jrtc27@...c27.com>, 
	Andrew Jones <ajones@...tanamicro.com>, linux-riscv@...ts.infradead.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-sunxi@...ts.linux.dev, linux-doc@...r.kernel.org, 
	linux-kselftest@...r.kernel.org, Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v10 02/14] dt-bindings: cpus: add a thead vlen register
 length property

Charlie Jenkins <charlie@...osinc.com> 於 2024年9月12日 週四 下午1:57寫道：
>
> Add a property analogous to the vlenb CSR so that software can detect
> the vector length of each CPU prior to it being brought online.
> Currently software has to assume that the vector length read from the
> boot CPU applies to all possible CPUs. On T-Head CPUs implementing
> pre-ratification vector, reading the th.vlenb CSR may produce an illegal
> instruction trap, so this property is required on such systems.
>
> Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Reviewed-by: Andy Chiu <andybnac@...il.com>

> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 8edc8261241a..c0cf6cf56749 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -26,6 +26,18 @@ description: |
>  allOf:
>    - $ref: /schemas/cpu.yaml#
>    - $ref: extensions.yaml
> +  - if:
> +      not:
> +        properties:
> +          compatible:
> +            contains:
> +              enum:
> +                - thead,c906
> +                - thead,c910
> +                - thead,c920
> +    then:
> +      properties:
> +        thead,vlenb: false
>
>  properties:
>    compatible:
> @@ -95,6 +107,13 @@ properties:
>      description:
>        The blocksize in bytes for the Zicboz cache operations.
>
> +  thead,vlenb:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      VLEN/8, the vector register length in bytes. This property is required on
> +      thead systems where the vector register length is not identical on all harts, or
> +      the vlenb CSR is not available.
> +
>    # RISC-V has multiple properties for cache op block sizes as the sizes
>    # differ between individual CBO extensions
>    cache-op-block-size: false
>
> --
> 2.45.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives