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Message-ID: <CADnq5_NiUmJ3K0cYcToDQ34D9zkEREfub6CBY3iC8515ss_E3A@mail.gmail.com>
Date: Wed, 2 Oct 2024 13:58:40 -0400
From: Alex Deucher <alexdeucher@...il.com>
To: Igor Artemiev <Igor.A.Artemiev@...t.ru>
Cc: Alex Deucher <alexander.deucher@....com>, 
	Christian König <christian.koenig@....com>, 
	Xinhui Pan <Xinhui.Pan@....com>, David Airlie <airlied@...il.com>, 
	Kenneth Feng <kenneth.feng@....com>, Simona Vetter <simona@...ll.ch>, amd-gfx@...ts.freedesktop.org, 
	dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org, 
	lvc-project@...uxtesting.org
Subject: Re: [PATCH v2] drm/amd/pm: check return value of amdgpu_irq_add_id()

Applied.  Thanks!

Alex

On Wed, Oct 2, 2024 at 9:28 AM Igor Artemiev <Igor.A.Artemiev@...t.ru> wrote:
>
> amdgpu_irq_ad_id() may fail and the irq handlers will not be registered.
> This patch adds error code check.
>
> Found by Linux Verification Center (linuxtesting.org) with static
> analysis tool SVACE.
>
> Signed-off-by: Igor Artemiev <Igor.A.Artemiev@...t.ru>
> ---
> v2: Remove the cast to struct amdgpu_device as Christian König
> <christian.koenig@....com> suggested.
>
>  .../drm/amd/pm/powerplay/hwmgr/smu_helper.c   | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
> index 79a566f3564a..50a3085c00aa 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
> @@ -647,28 +647,41 @@ int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr)
>  {
>         struct amdgpu_irq_src *source =
>                 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
> +       int ret;
>
>         if (!source)
>                 return -ENOMEM;
>
>         source->funcs = &smu9_irq_funcs;
>
> -       amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
> +       ret = amdgpu_irq_add_id(hwmgr->adev,
>                         SOC15_IH_CLIENTID_THM,
>                         THM_9_0__SRCID__THM_DIG_THERM_L2H,
>                         source);
> -       amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
> +       if (ret)
> +               goto err;
> +
> +       ret = amdgpu_irq_add_id(hwmgr->adev,
>                         SOC15_IH_CLIENTID_THM,
>                         THM_9_0__SRCID__THM_DIG_THERM_H2L,
>                         source);
> +       if (ret)
> +               goto err;
>
>         /* Register CTF(GPIO_19) interrupt */
> -       amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
> +       ret = amdgpu_irq_add_id(hwmgr->adev,
>                         SOC15_IH_CLIENTID_ROM_SMUIO,
>                         SMUIO_9_0__SRCID__SMUIO_GPIO19,
>                         source);
> +       if (ret)
> +               goto err;
>
>         return 0;
> +
> +err:
> +       kfree(source);
> +
> +       return ret;
>  }
>
>  void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
> --
> 2.39.2
>

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