linux-kernel - Re: [PATCH] arm64/mm: Change pgattr_change_is_safe() arguments as pteval

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Message-ID: <91fa29e9-0659-4837-8261-d8b2865e6132@arm.com>
Date: Wed, 2 Oct 2024 10:13:45 +0100
From: Ryan Roberts <ryan.roberts@....com>
To: Anshuman Khandual <anshuman.khandual@....com>,
 linux-arm-kernel@...ts.infradead.org
Cc: Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
 Mark Rutland <mark.rutland@....com>, Ard Biesheuvel <ardb@...nel.org>,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64/mm: Change pgattr_change_is_safe() arguments as
 pteval_t

On 01/10/2024 05:58, Anshuman Khandual wrote:
> pgattr_change_is_safe() processes two distinct page table entries that just
> happen to be 64 bits for all levels. This changes both arguments to reflect
> the actual data type being processed in the function.
> 
> This change is important when moving to FEAT_D128 based 128 bit page tables
> because it makes it simple to change the entry size in one place.
> 
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will@...nel.org>
> Cc: Mark Rutland <mark.rutland@....com>
> Cc: Ard Biesheuvel <ardb@...nel.org>
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> Reviewed-by: Ryan Roberts <ryan.roberts@....com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@....com>

LGTM!

Reviewed-by: Ryan Roberts <ryan.roberts@....com>

> ---
> This applies on v6.12-rc1
> 
>  arch/arm64/include/asm/pgtable.h | 2 +-
>  arch/arm64/mm/mmu.c              | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index c329ea061dc9..d56dbe5742d6 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -338,7 +338,7 @@ static inline pte_t __ptep_get(pte_t *ptep)
>  }
>  
>  extern void __sync_icache_dcache(pte_t pteval);
> -bool pgattr_change_is_safe(u64 old, u64 new);
> +bool pgattr_change_is_safe(pteval_t old, pteval_t new);
>  
>  /*
>   * PTE bits configuration in the presence of hardware Dirty Bit Management
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index e55b02fbddc8..c1b2d0dc3078 100644
> --- a/arch/arm64/mm/mmu.c
> +++ b/arch/arm64/mm/mmu.c
> @@ -119,7 +119,7 @@ static phys_addr_t __init early_pgtable_alloc(int shift)
>  	return phys;
>  }
>  
> -bool pgattr_change_is_safe(u64 old, u64 new)
> +bool pgattr_change_is_safe(pteval_t old, pteval_t new)
>  {
>  	/*
>  	 * The following mapping attributes may be updated in live