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Message-ID: <20241002-private-unequal-33cfa6101338@spud>
Date: Wed, 2 Oct 2024 11:47:58 +0100
From: Conor Dooley <conor@...nel.org>
To: linux-kernel@...r.kernel.org
Cc: conor@...nel.org,
Conor Dooley <conor.dooley@...rochip.com>,
Daire McNamara <daire.mcnamara@...rochip.com>,
pierre-henry.moussay@...rochip.com,
valentina.fernandezalanis@...rochip.com,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Jassi Brar <jassisinghbrar@...il.com>,
Lee Jones <lee@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Neil Armstrong <neil.armstrong@...aro.org>,
Jerome Brunet <jbrunet@...libre.com>,
Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
linux-riscv@...ts.infradead.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-amlogic@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v1 00/11] Redo PolarFire SoC's mailbox/clock devicestrees and related code
From: Conor Dooley <conor.dooley@...rochip.com>
Yo,
Here's something that I've been mulling over for a while, since I
started to understand how devicetree stuff was "meant" to be done.
There'd been little reason to actually press forward with it, because it
is fairly disruptive. I've finally opted to do it, because a user has
come along with a hwmon driver that needs to access the same register
region as the mailbox and the author is not keen on using the aux bus,
and because I do not want the new pic64gx SoC that's based on PolarFire
SoC to use bindings etc that I know to be incorrect.
Given backwards compatibility needs to be maintained, this patch series
isn't the prettiest thing I have ever written. The reset driver needs to
retain support for the auxiliary bus, which looks a bit mess, but not
much can be done there. The mailbox and clock drivers both have to have
an "old probe" function to handle the old layout. Thankfully in the
clock driver, the Meson clk-regmap support can be used to identically
handle both old and new devicetree formats - but using a regmap in the
mailbox driver was only really possible for the new format, so the code
there is unfortunately a bit of an if/else mess that I'm both not proud
of, nor really sure is worth "improving".
The series should be pretty splitable per subsystem, only the dts change
has some sort of dependency, but I'll not be applying that till
everything else is in Linus' tree, so that's not a big deal.
I've got all the Meson clock folks on CC, given I am moving their
clk-regmap implementation to common code. There were one or two things I
didn't really like about the implementation, but it is better than the
Qualcomm one IMO and creating a third copy of clk-regmap is certainly
not an improvement on having two copies!
I don't really want this stuff in stable, hence a lack of cc: stable
anywhere here, since what's currently in the tree works fine for the
currently supported hardware.
AFAIK, the only other project affected here is U-Boot - I've got some
WIP work that I need to rebase and send for it before the dts patches
here will be applied:
https://github.com/ConchuOD/u-boot/commits/syscon-clocks/
I previously submitted this as an RFC, only to Lee and the dt list, in
order to get some feedback on the syscon/mfd bindings:
https://lore.kernel.org/all/20240815-shindig-bunny-fd42792d638a@spud/
I'm not really going to bother with a proper changelog, since that was
submitted with lots of WIP code to get answers to some questions. The
main change was "removing" some of the child nodes of the syscons.
Cheers,
Conor.
CC: Conor Dooley <conor.dooley@...rochip.com>
CC: Daire McNamara <daire.mcnamara@...rochip.com>
CC: pierre-henry.moussay@...rochip.com
CC: valentina.fernandezalanis@...rochip.com
CC: Michael Turquette <mturquette@...libre.com>
CC: Stephen Boyd <sboyd@...nel.org>
CC: Rob Herring <robh@...nel.org>
CC: Krzysztof Kozlowski <krzk+dt@...nel.org>
CC: Jassi Brar <jassisinghbrar@...il.com>
CC: Lee Jones <lee@...nel.org>
CC: Paul Walmsley <paul.walmsley@...ive.com>
CC: Palmer Dabbelt <palmer@...belt.com>
CC: Albert Ou <aou@...s.berkeley.edu>
CC: Neil Armstrong <neil.armstrong@...aro.org>
CC: Jerome Brunet <jbrunet@...libre.com>
CC: Kevin Hilman <khilman@...libre.com>
CC: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
CC: Philipp Zabel <p.zabel@...gutronix.de>
CC: linux-riscv@...ts.infradead.org
CC: linux-clk@...r.kernel.org
CC: devicetree@...r.kernel.org
CC: linux-kernel@...r.kernel.org
CC: linux-amlogic@...ts.infradead.org
CC: linux-arm-kernel@...ts.infradead.org
Conor Dooley (11):
dt-bindings: mailbox: mpfs: fix reg properties
mailbox: mpfs: support new, syscon based, devicetree configuration
dt-bindings: mfd: syscon document the non simple-mfd syscon on
PolarFire SoC
dt-bindings: soc: microchip: document the two simple-mfd syscons on
PolarFire SoC
soc: microchip: add mfd drivers for two syscon regions on PolarFire
SoC
reset: mpfs: add non-auxiliary bus probing
dt-bindings: clk: microchip: mpfs: remove first reg region
clk: move meson clk-regmap implementation to common code
clk: microchip: mpfs: use regmap clock types
riscv: dts: microchip: fix mailbox description
riscv: dts: microchip: convert clock and reset to use syscon
.../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++---
.../mailbox/microchip,mpfs-mailbox.yaml | 13 +-
.../devicetree/bindings/mfd/syscon.yaml | 2 +
.../microchip/microchip,mpfs-control-scb.yaml | 44 +++++++
.../microchip,mpfs-mss-top-sysreg.yaml | 54 +++++++++
arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 ++++--
drivers/clk/Kconfig | 4 +
drivers/clk/Makefile | 1 +
drivers/clk/{meson => }/clk-regmap.c | 2 +-
drivers/clk/meson/Kconfig | 46 ++++---
drivers/clk/meson/Makefile | 1 -
drivers/clk/meson/a1-peripherals.c | 2 +-
drivers/clk/meson/a1-pll.c | 2 +-
drivers/clk/meson/axg-aoclk.c | 2 +-
drivers/clk/meson/axg-audio.c | 2 +-
drivers/clk/meson/axg.c | 2 +-
drivers/clk/meson/c3-peripherals.c | 2 +-
drivers/clk/meson/c3-pll.c | 2 +-
drivers/clk/meson/clk-cpu-dyndiv.c | 2 +-
drivers/clk/meson/clk-dualdiv.c | 2 +-
drivers/clk/meson/clk-mpll.c | 2 +-
drivers/clk/meson/clk-phase.c | 2 +-
drivers/clk/meson/clk-pll.c | 2 +-
drivers/clk/meson/g12a-aoclk.c | 2 +-
drivers/clk/meson/g12a.c | 2 +-
drivers/clk/meson/gxbb-aoclk.c | 2 +-
drivers/clk/meson/gxbb.c | 2 +-
drivers/clk/meson/meson-aoclk.h | 2 +-
drivers/clk/meson/meson-eeclk.c | 2 +-
drivers/clk/meson/meson-eeclk.h | 2 +-
drivers/clk/meson/meson8-ddr.c | 2 +-
drivers/clk/meson/meson8b.c | 2 +-
drivers/clk/meson/s4-peripherals.c | 2 +-
drivers/clk/meson/s4-pll.c | 2 +-
drivers/clk/meson/sclk-div.c | 2 +-
drivers/clk/meson/vclk.h | 2 +-
drivers/clk/meson/vid-pll-div.c | 2 +-
drivers/clk/microchip/Kconfig | 3 +
drivers/clk/microchip/clk-mpfs.c | 114 +++++++++++++-----
drivers/mailbox/Kconfig | 1 +
drivers/mailbox/mailbox-mpfs.c | 87 ++++++++++---
drivers/reset/reset-mpfs.c | 83 +++++++++++--
drivers/soc/microchip/Kconfig | 13 ++
drivers/soc/microchip/Makefile | 1 +
drivers/soc/microchip/mpfs-control-scb.c | 45 +++++++
drivers/soc/microchip/mpfs-mss-top-sysreg.c | 48 ++++++++
.../meson => include/linux/clk}/clk-regmap.h | 0
47 files changed, 541 insertions(+), 143 deletions(-)
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-control-scb.yaml
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
rename drivers/clk/{meson => }/clk-regmap.c (99%)
create mode 100644 drivers/soc/microchip/mpfs-control-scb.c
create mode 100644 drivers/soc/microchip/mpfs-mss-top-sysreg.c
rename {drivers/clk/meson => include/linux/clk}/clk-regmap.h (100%)
--
2.45.2
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