linux-kernel - RE: [PATCH 1/2] irqchip/gic-v3-its: Share ITS tables with a non-trusted hypervisor

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Message-ID: <875xqay61a.ffs@tglx>
Date: Wed, 02 Oct 2024 15:43:13 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Michael Kelley <mhklinux@...look.com>, Steven Price
 <steven.price@....com>, Marc Zyngier <maz@...nel.org>
Cc: "linux-arm-kernel@...ts.infradead.org"
 <linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
 <linux-kernel@...r.kernel.org>, Will Deacon <will@...nel.org>, Suzuki K
 Poulose <suzuki.poulose@....com>
Subject: RE: [PATCH 1/2] irqchip/gic-v3-its: Share ITS tables with a
 non-trusted hypervisor

On Mon, Sep 09 2024 at 03:47, Michael Kelley wrote:
>> +	ret = set_memory_decrypted((unsigned long)page_address(page),
>> +				   1 << order);
>> +	if (WARN_ON(ret))
>
> On the x86 side, the WARN is done in the implementation of
> set_memory_decrypted()/encrypted() so that each call site doesn't
> need to do the WARN. Each call site must only leak the memory
> if the return value indicates other than success. There are call sites
> in architecture neutral code (such as for swiotlb and DMA direct)
> that expect the WARN is in set_memory_decrypted()/encrypted().
> To recap a previous discussion, we want the WARN for notification,
> but also so the most security-conscious users can set
> kernel.panic_on_warn=1 to stop further processing if there are
> problems in the decryption/encryption operation.

What's the resolution of this?

Thanks,

        tglx