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Message-ID: <Zv7wz45VRIDeFd4K@lizhi-Precision-Tower-5810>
Date: Thu, 3 Oct 2024 15:30:23 -0400
From: Frank Li <Frank.li@....com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: Rob Herring <robh@...nel.org>, Saravana Kannan <saravanak@...gle.com>,
Jingoo Han <jingoohan1@...il.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Richard Zhu <hongxing.zhu@....com>,
Lucas Stach <l.stach@...gutronix.de>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, imx@...ts.linux.dev
Subject: Re: [PATCH v3 2/3] PCI: dwc: Using parent_bus_addr in of_range to
eliminate cpu_addr_fixup()y
On Thu, Oct 03, 2024 at 11:21:06AM +0530, Manivannan Sadhasivam wrote:
> On Mon, Sep 30, 2024 at 02:44:54PM -0400, Frank Li wrote:
> > parent_bus_addr in struct of_range can indicate address information just
> > ahead of PCIe controller. Most system's bus fabric use 1:1 map between
> > input and output address. but some hardware like i.MX8QXP doesn't use 1:1
> > map. See below diagram:
> >
> > ┌─────────┐ ┌────────────┐
> > ┌─────┐ │ │ IA: 0x8ff0_0000 │ │
> > │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │
> > └─────┘ │ │ │ IA: 0x8ff8_0000 │ │ │
> > CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │
> > 0x7ff0_0000─┼───┘ │ │ │ │ │ │
> > │ │ │ │ │ │ │ PCI Addr
> > 0x7ff8_0000─┼──────┘ │ │ └──► CfgSpace ─┼────────────►
> > │ │ │ │ │ 0
> > 0x7000_0000─┼────────►├─────────┐ │ │ │
> > └─────────┘ │ └──────► IOSpace ─┼────────────►
> > BUS Fabric │ │ │ 0
> > │ │ │
> > └──────────► MemSpace ─┼────────────►
> > IA: 0x8000_0000 │ │ 0x8000_0000
> > └────────────┘
> >
> > bus@...00000 {
> > compatible = "simple-bus";
> > #address-cells = <1>;
> > #size-cells = <1>;
> > ranges = <0x5f000000 0x0 0x5f000000 0x21000000>,
> > <0x80000000 0x0 0x70000000 0x10000000>;
>
> Does this address translation apply to all peripherals in the bus or just PCIe?
No difference. Actually only PCIe under this bus fabric.
> If it is just PCIe, why can't you encode the mapping in the below PCIe node
> 'ranges' property itself?
Even it change by bus fabric, you still treat it as by PCIe. But it can't
remove ugly .cpu_fixes_up() function, becuase IO range can't know actual
address input to PCI controller.
If dt correct descript hardware behavior, we will not need .cpu_fixed_up()
at all.
>
> - Mani
>
> >
> > pcie@...10000 {
> > compatible = "fsl,imx8q-pcie";
> > reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>;
> > reg-names = "dbi", "config";
> > #address-cells = <3>;
> > #size-cells = <2>;
> > device_type = "pci";
> > bus-range = <0x00 0xff>;
> > ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>,
> > <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>;
> > ...
> > };
> > };
> >
> > Term internal address (IA) here means the address just before PCIe
> > controller. After ATU use this IA instead CPU address, cpu_addr_fixup() can
> > be removed.
> >
> > Signed-off-by: Frank Li <Frank.Li@....com>
> > ---
> > Change from v2 to v3
> > - %s/cpu_untranslate_addr/parent_bus_addr/g
> > - update diagram.
> > - improve commit message.
> >
> > Change from v1 to v2
> > - update because patch1 change get untranslate address method.
> > - add using_dtbus_info in case break back compatibility for exited platform.
> > ---
> > drivers/pci/controller/dwc/pcie-designware-host.c | 42 +++++++++++++++++++++++
> > drivers/pci/controller/dwc/pcie-designware.h | 8 +++++
> > 2 files changed, 50 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > index 3e41865c72904..823ff42c2e2c9 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > @@ -418,6 +418,34 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
> > }
> > }
> >
> > +static int dw_pcie_get_untranslate_addr(struct dw_pcie *pci, resource_size_t pci_addr,
> > + resource_size_t *i_addr)
> > +{
> > + struct device *dev = pci->dev;
> > + struct device_node *np = dev->of_node;
> > + struct of_range_parser parser;
> > + struct of_range range;
> > + int ret;
> > +
> > + if (!pci->using_dtbus_info) {
> > + *i_addr = pci_addr;
> > + return 0;
> > + }
> > +
> > + ret = of_range_parser_init(&parser, np);
> > + if (ret)
> > + return ret;
> > +
> > + for_each_of_pci_range(&parser, &range) {
> > + if (pci_addr == range.bus_addr) {
> > + *i_addr = range.parent_bus_addr;
> > + break;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > int dw_pcie_host_init(struct dw_pcie_rp *pp)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > @@ -427,6 +455,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> > struct resource_entry *win;
> > struct pci_host_bridge *bridge;
> > struct resource *res;
> > + int index;
> > int ret;
> >
> > raw_spin_lock_init(&pp->lock);
> > @@ -440,6 +469,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> > pp->cfg0_size = resource_size(res);
> > pp->cfg0_base = res->start;
> >
> > + if (pci->using_dtbus_info) {
> > + index = of_property_match_string(np, "reg-names", "config");
> > + if (index < 0)
> > + return -EINVAL;
> > + of_property_read_reg(np, index, &pp->cfg0_base, NULL);
> > + }
> > +
> > pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res);
> > if (IS_ERR(pp->va_cfg0_base))
> > return PTR_ERR(pp->va_cfg0_base);
> > @@ -462,6 +498,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> > pp->io_base = pci_pio_to_address(win->res->start);
> > }
> >
> > + if (dw_pcie_get_untranslate_addr(pci, pp->io_bus_addr, &pp->io_base))
> > + return -ENODEV;
> > +
> > /* Set default bus ops */
> > bridge->ops = &dw_pcie_ops;
> > bridge->child_ops = &dw_child_pcie_ops;
> > @@ -733,6 +772,9 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > atu.cpu_addr = entry->res->start;
> > atu.pci_addr = entry->res->start - entry->offset;
> >
> > + if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr))
> > + return -EINVAL;
> > +
> > /* Adjust iATU size if MSG TLP region was allocated before */
> > if (pp->msg_res && pp->msg_res->parent == entry->res)
> > atu.size = resource_size(entry->res) -
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index c189781524fb8..e22d32b5a5f19 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -464,6 +464,14 @@ struct dw_pcie {
> > struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];
> > struct gpio_desc *pe_rst;
> > bool suspended;
> > + /*
> > + * Use device tree 'ranges' property of bus node instead using
> > + * cpu_addr_fixup(). Some old platform dts 'ranges' in bus node may not
> > + * reflect real hardware's behavior. In case break these platform back
> > + * compatibility, add below flags. Set it true if dts already correct
> > + * indicate bus fabric address convert.
> > + */
> > + bool using_dtbus_info;
> > };
> >
> > #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
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