linux-kernel - Re: [PATCH v4 2/2] i2c: dwsignware: determine HS tHIGH and tLOW based on HW parameters

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Message-ID: <Zv6C8Zj4NabZf_PM@smile.fi.intel.com>
Date: Thu, 3 Oct 2024 14:41:37 +0300
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Michael Wu <michael.wu@...ron.us>
Cc: Andi Shyti <andi.shyti@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Jarkko Nikula <jarkko.nikula@...ux.intel.com>,
	Mika Westerberg <mika.westerberg@...ux.intel.com>,
	Jan Dabros <jsd@...ihalf.com>, linux-i2c@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	Morgan Chang <morgan.chang@...ron.us>, mvp.kutali@...il.com
Subject: Re: [PATCH v4 2/2] i2c: dwsignware: determine HS tHIGH and tLOW
 based on HW parameters

On Thu, Oct 03, 2024 at 07:15:24PM +0800, Michael Wu wrote:
> In commit 35eba185fd1a ("i2c: designware: Calculate SCL timing parameter
> for High Speed Mode") the SCL high period count and low period count for
> high speed mode are calculated based on fixed tHIGH = 160 and tLOW = 120.
> However, the set of two fixed values is only applicable to the combination
> of hardware parameters IC_CAP_LOADING is 400 and IC_CLK_FREQ_OPTIMIZATION
> is true. Outside of this combination, the SCL frequency may not reach
> 3.4 MHz because the fixed tHIGH and tLOW are not small enough.
> 
> If IC_CAP_LOADING is 400, it means the bus capacitance is 400pF;
> Otherwise, 100 pF. If IC_CLK_FREQ_OPTIMIZATION is true, it means that the
> hardware reduces its internal clock frequency by reducing the internal
> latency required to generate the high period and low period of the SCL line.
> 
> Section 3.15.4.5 in DesignWare DW_apb_i2b Databook v2.03 says that when
> IC_CLK_FREQ_OPTIMIZATION = 0,
> 
>     MIN_SCL_HIGHtime = 60 ns for 3.4 Mbps, bus loading = 100pF
> 		     = 120 ns for 3.4 Mbps, bus loading = 400pF
>     MIN_SCL_LOWtime = 160 ns for 3.4 Mbps, bus loading = 100pF
> 		    = 320 ns for 3.4 Mbps, bus loading = 400pF
> 
> and section 3.15.4.6 says that when IC_CLK_FREQ_OPTIMIZATION = 1,
> 
>     MIN_SCL_HIGHtime = 60 ns for 3.4 Mbps, bus loading = 100pF
> 		     = 160 ns for 3.4 Mbps, bus loading = 400pF
>     MIN_SCL_LOWtime = 120 ns for 3.4 Mbps, bus loading = 100pF
> 		    = 320 ns for 3.4 Mbps, bus loading = 400pF
> 
> In order to calculate more accurate SCL high period count and low period
> count for high speed mode, two hardware parameters IC_CAP_LOADING and
> IC_CLK_FREQ_OPTIMIZATION must be considered together. Since there're no
> registers controlliing these these two hardware parameters, users can
> declare them in the device tree so that the driver can obtain them.

As long as DT schema (new properties) is accepted, this LGTM now,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>

-- 
With Best Regards,
Andy Shevchenko