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Message-ID: <20241004182200.3670903-35-sashal@kernel.org> Date: Fri, 4 Oct 2024 14:20:33 -0400 From: Sasha Levin <sashal@...nel.org> To: linux-kernel@...r.kernel.org, stable@...r.kernel.org Cc: Jisheng Zhang <jszhang@...nel.org>, Cyril Bur <cyrilbur@...storrent.com>, Palmer Dabbelt <palmer@...osinc.com>, Sasha Levin <sashal@...nel.org>, paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu, samitolvanen@...gle.com, cleger@...osinc.com, ajones@...tanamicro.com, debug@...osinc.com, andy.chiu@...ive.com, antonb@...storrent.com, linux-riscv@...ts.infradead.org Subject: [PATCH AUTOSEL 6.10 35/70] riscv: avoid Imbalance in RAS From: Jisheng Zhang <jszhang@...nel.org> [ Upstream commit 8f1534e7440382d118c3d655d3a6014128b2086d ] Inspired by[1], modify the code to remove the code of modifying ra to avoid imbalance RAS (return address stack) which may lead to incorret predictions on return. Link: https://lore.kernel.org/linux-riscv/20240607061335.2197383-1-cyrilbur@tenstorrent.com/ [1] Signed-off-by: Jisheng Zhang <jszhang@...nel.org> Reviewed-by: Cyril Bur <cyrilbur@...storrent.com> Link: https://lore.kernel.org/r/20240720170659.1522-1-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@...osinc.com> Signed-off-by: Sasha Levin <sashal@...nel.org> --- arch/riscv/kernel/entry.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 68a24cf9481af..d143dde853b51 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -232,8 +232,8 @@ SYM_CODE_START(ret_from_fork) jalr s0 1: move a0, sp /* pt_regs */ - la ra, ret_from_exception - tail syscall_exit_to_user_mode + call syscall_exit_to_user_mode + j ret_from_exception SYM_CODE_END(ret_from_fork) #ifdef CONFIG_IRQ_STACKS -- 2.43.0
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