linux-kernel - Re: [PATCH V4 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574

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Message-ID: <29b84acf-2c57-4b0e-81f0-82eb6c1e5b18@quicinc.com>
Date: Fri, 4 Oct 2024 13:25:52 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: Devi Priya <quic_devipriy@...cinc.com>, Andrew Lunn <andrew@...n.ch>
CC: <andersson@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>,
        <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <konrad.dybcio@...aro.org>, <catalin.marinas@....com>,
        <will@...nel.org>, <p.zabel@...gutronix.de>,
        <richardcochran@...il.com>, <geert+renesas@...der.be>,
        <dmitry.baryshkov@...aro.org>, <neil.armstrong@...aro.org>,
        <arnd@...db.de>, <m.szyprowski@...sung.com>, <nfraprado@...labora.com>,
        <u-kumar1@...com>, <linux-arm-msm@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
        <netdev@...r.kernel.org>
Subject: Re: [PATCH V4 5/7] clk: qcom: Add NSS clock Controller driver for
 IPQ9574



On 6/26/2024 8:09 PM, Devi Priya wrote:
> 
> 
> On 6/25/2024 8:09 PM, Andrew Lunn wrote:
>>> +static struct clk_alpha_pll ubi32_pll_main = {
>>> +    .offset = 0x28000,
>>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>> +    .flags = SUPPORTS_DYNAMIC_UPDATE,
>>> +    .clkr = {
>>> +        .hw.init = &(const struct clk_init_data) {
>>> +            .name = "ubi32_pll_main",
>>> +            .parent_data = &(const struct clk_parent_data) {
>>> +                .index = DT_XO,
>>> +            },
>>> +            .num_parents = 1,
>>> +            .ops = &clk_alpha_pll_huayra_ops,
>>> +        },
>>> +    },
>>> +};
>>> +
>>> +static struct clk_alpha_pll_postdiv ubi32_pll = {
>>> +    .offset = 0x28000,
>>> +    .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
>>> +    .width = 2,
>>> +    .clkr.hw.init = &(const struct clk_init_data) {
>>> +        .name = "ubi32_pll",
>>> +        .parent_hws = (const struct clk_hw *[]) {
>>> +            &ubi32_pll_main.clkr.hw
>>> +        },
>>> +        .num_parents = 1,
>>> +        .ops = &clk_alpha_pll_postdiv_ro_ops,
>>> +        .flags = CLK_SET_RATE_PARENT,
>>> +    },
>>> +};
>>
>> Can these structures be made const? You have quite a few different
>> structures in this driver, some of which are const, and some which are
>> not.
>>
> Sure, will check and update this in V6
> 
> Thanks,
> Devi Priya
>>     Andrew
>>

Hi Andrew,

Sorry for the delayed response.

The ubi32_pll_main structure should be passed to clk_alpha_pll_configure() API to configure UBI32 PLL. clk_alpha_pll_configure() API expects a non-const structure. Declaring it as const will result in the following compilation warning

drivers/clk/qcom/nsscc-ipq9574.c:3067:26: warning: passing argument 1 of ‘clk_alpha_pll_configure’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
                          ^
In file included from drivers/clk/qcom/nsscc-ipq9574.c:22:0:
drivers/clk/qcom/clk-alpha-pll.h:200:6: note: expected ‘struct clk_alpha_pll *’ but argument is of type ‘const struct clk_alpha_pll *’
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
      ^~~~~~~~~~~~~~~~~~~~~~~

The ubi32_pll is the source for nss_cc_ubi0_clk_src, nss_cc_ubi1_clk_src, nss_cc_ubi2_clk_src, nss_cc_ubi3_clk_src. Therefore, to register ubi32_pll with clock framework, it should be assigned to UBI32_PLL index of nss_cc_ipq9574_clocks array. This assignment will result in the following compilation warning if the ubi32_pll structure is declared as const.

drivers/clk/qcom/nsscc-ipq9574.c:2893:16: warning: initialization discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
  [UBI32_PLL] = &ubi32_pll.clkr,

Thanks & Regards,
Manikanta.