linux-kernel - Re: [PATCH V3 4/7] clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC

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Message-ID: <1ac5e0e5-06c1-4930-8c03-f465d6e07848@quicinc.com>
Date: Fri, 4 Oct 2024 16:51:57 +0530
From: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
To: Sricharan R <quic_srichara@...cinc.com>, <andersson@...nel.org>,
        <konradybcio@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>,
        <ulf.hansson@...aro.org>, <linus.walleij@...aro.org>,
        <catalin.marinas@....com>, <p.zabel@...gutronix.de>,
        <geert+renesas@...der.be>, <dmitry.baryshkov@...aro.org>,
        <neil.armstrong@...aro.org>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-mmc@...r.kernel.org>,
        <linux-gpio@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>
CC: <quic_varada@...cinc.com>
Subject: Re: [PATCH V3 4/7] clk: qcom: add Global Clock controller (GCC)
 driver for IPQ5424 SoC



On 10/4/2024 3:53 PM, Sricharan R wrote:
> From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> 
> Add support for the global clock controller found on IPQ5424 SoC.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Co-developed-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> ---
>   [V3] Added Reviewed tag
> 
>   drivers/clk/qcom/Kconfig       |    8 +
>   drivers/clk/qcom/Makefile      |    1 +
>   drivers/clk/qcom/gcc-ipq5424.c | 3309 ++++++++++++++++++++++++++++++++
>   3 files changed, 3318 insertions(+)
>   create mode 100644 drivers/clk/qcom/gcc-ipq5424.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index a3e2a09e2105..6a576bc2301c 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -213,6 +213,14 @@ config IPQ_GCC_5332
>   	  Say Y if you want to use peripheral devices such as UART, SPI,
>   	  i2c, USB, SD/eMMC, etc.
>   
> +config IPQ_GCC_5424
> +	tristate "IPQ5424 Global Clock Controller"
> +	depends on ARM64 || COMPILE_TEST
> +	help
> +	  Support for the global clock controller on ipq5424 devices.
> +	  Say Y if you want to use peripheral devices such as UART, SPI,
> +	  i2c, USB, SD/eMMC, etc.
> +
>   config IPQ_GCC_6018
>   	tristate "IPQ6018 Global Clock Controller"
>   	help
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 2b378667a63f..d58ba0f9a482 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
>   obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
>   obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
>   obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
> +obj-$(CONFIG_IPQ_GCC_5424) += gcc-ipq5424.o
>   obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>   obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>   obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c
> new file mode 100644
> index 000000000000..3458c1c98bb7
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq5424.c
> @@ -0,0 +1,3309 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
> +#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "clk-regmap-phy-mux.h"
> +#include "common.h"
> +#include "reset.h"
> +
> +enum {
> +	DT_XO,
> +	DT_SLEEP_CLK,
> +	DT_PCIE30_PHY0_PIPE_CLK,
> +	DT_PCIE30_PHY1_PIPE_CLK,
> +	DT_PCIE30_PHY2_PIPE_CLK,
> +	DT_PCIE30_PHY3_PIPE_CLK,
> +	DT_USB_PCIE_WRAPPER_PIPE_CLK,
> +};
> +
> +enum {
> +	P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
> +	P_GPLL0_OUT_AUX,
> +	P_GPLL0_OUT_MAIN,
> +	P_GPLL2_OUT_AUX,
> +	P_GPLL2_OUT_MAIN,
> +	P_GPLL4_OUT_AUX,
> +	P_GPLL4_OUT_MAIN,
> +	P_SLEEP_CLK,
> +	P_XO,
> +	P_USB3PHY_0_PIPE,
> +};
> +


<snip>

> +
> +static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] = {
> +	F(960000, P_XO, 10, 2, 5),
> +	F(4800000, P_XO, 5, 0, 0),
> +	F(9600000, P_XO, 2, 4, 5),
> +	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
> +	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> +	F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
> +	{ }
> +};
> +

There are few more frequencies got added to this table. Can we 
incorporate that as well?

Thanks, Kathiravan T.