linux-kernel - Re: [PATCH 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <42ndts6wuoor3tbt3uv5kuco37kc6bnnoepqtauqosw2gg2xn7@7hfdc6wgvlsm>
Date: Sat, 5 Oct 2024 08:46:37 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Conor Dooley <conor@...nel.org>, Inochi Amaoto <inochiama@...il.com>
Cc: Chen Wang <unicorn_wang@...look.com>, 
	Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, 
	Albert Ou <aou@...s.berkeley.edu>, Peter Zijlstra <peterz@...radead.org>, 
	Inochi Amaoto <inochiama@...look.com>, Guo Ren <guoren@...nel.org>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, Hal Feng <hal.feng@...rfivetech.com>, 
	Heikki Krogerus <heikki.krogerus@...ux.intel.com>, Geert Uytterhoeven <geert+renesas@...der.be>, 
	Yixun Lan <dlan@...too.org>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-riscv@...ts.infradead.org
Subject: Re: [PATCH 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044
 ACLINT SSWI

On Fri, Oct 04, 2024 at 04:44:22PM +0100, Conor Dooley wrote:
> On Fri, Oct 04, 2024 at 04:05:55PM +0800, Inochi Amaoto wrote:
> > Sophgo SG2044 has a new version of T-HEAD C920, which implement
> > a fully featured ACLINT device. This ACLINT has an extra SSWI
> > field to support fast S-mode IPI.
> > 
> > Add necessary compatible string for the T-HEAD ACLINT sswi device.
> > 
> > Signed-off-by: Inochi Amaoto <inochiama@...il.com>
> > ---
> >  .../thead,c900-aclint-sswi.yaml               | 58 +++++++++++++++++++
> >  1 file changed, 58 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
> > new file mode 100644
> > index 000000000000..0106fbf3ea1f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device
> > +
> > +maintainers:
> > +  - Inochi Amaoto <inochiama@...look.com>
> > +
> > +description:
> > +  The SSWI device is a part of the riscv ACLINT device. It provides
> > +  supervisor-level IPI functionality for a set of HARTs on a RISC-V
> > +  platform. It provides a register to set an IPI (SETSSIP) for each
> > +  HART connected to the SSWI device.
> 
> If it is part of the aclint, why should it have a separate node, rather
> than be part of the existing aclint node as a third reg property?

For aclint, the current nodes that have documented are mswi and mtime.
Since the mtime is a M-mode time source, it is not suitable to add the
sswi reg into this device. For mswi, it is OK to add a sswi reg, but
this will cause problem while checking "interrupt-extend". Do we just
double the maxItem? Or just left it unchanged?

Another reason to add it as a separate node is that the draft says
sswi can be multiple. If we add this device by adding reg. It will be
hard if we have multiple sswi devices but one mswi device.

Regard,
Inochi