[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <ZwFJvV7lrFStWD-r@finisterre.sirena.org.uk>
Date: Sat, 5 Oct 2024 15:14:21 +0100
From: Mark Brown <broonie@...nel.org>
To: Marc Zyngier <maz@...nel.org>
Cc: Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Oliver Upton <oliver.upton@...ux.dev>,
Joey Gouly <joey.gouly@....com>,
Suzuki K Poulose <suzuki.poulose@....com>,
Shuah Khan <shuah@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-doc@...r.kernel.org, kvmarm@...ts.linux.dev,
linux-kselftest@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v14 4/5] KVM: arm64: Set PSTATE.EXLOCK when entering an
exception
On Sat, Oct 05, 2024 at 01:36:09PM +0100, Marc Zyngier wrote:
> Mark Brown <broonie@...nel.org> wrote:
> > + // PSTATE.EXLOCK is set to 0 upon any exception to a higher
> > + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
> > + // exception level. See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a.
> > + if (kvm_has_gcs(vcpu->kvm) &&
> > + (target_mode & PSR_EL_MASK) == (mode & PSR_EL_MASK)) {
> > + u64 gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1);
> No, please. This only works by luck when a guest has AArch32 EL0, and
> creates more havoc on a NV guest. In general, this PSR_EL_MASK creates
> more problem than anything else, and doesn't fit the rest of the code.
You say luck, I say careful architecture definition but sure.
> So this needs to:
> - explicitly only apply to exceptions from AArch64
> - handle exception from EL2, since this helper already deals with that
> The latter point of course means introducing GCSCR_EL2 (and everything
> that depends on it, such as the trap handling).
For clarity, which trap handling specifically?
Download attachment "signature.asc" of type "application/pgp-signature" (489 bytes)
Powered by blists - more mailing lists