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Message-ID: <CAFULd4ZZxrJvJ9gF5tC-m-tmcDMvVM3te4xc7vnbF_OFU0D2=A@mail.gmail.com>
Date: Sun, 6 Oct 2024 10:06:33 +0200
From: Uros Bizjak <ubizjak@...il.com>
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: "H. Peter Anvin" <hpa@...or.com>, Ard Biesheuvel <ardb@...nel.org>, Ard Biesheuvel <ardb+git@...gle.com>,
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Subject: Re: [RFC PATCH 25/28] x86: Use PIE codegen for the core kernel
On Sun, Oct 6, 2024 at 2:00 AM Linus Torvalds
<torvalds@...ux-foundation.org> wrote:
>
> On Sat, 5 Oct 2024 at 16:37, H. Peter Anvin <hpa@...or.com> wrote:
> >
> > Sadly, that is not correct; neither gcc nor clang uses lea:
>
> Looking around, this may be intentional. At least according to Agner,
> several cores do better at "mov immediate" compared to "lea".
>
> Eg a RIP-relative LEA on Zen 2 gets a throughput of two per cycle, but
> a "MOV r,i" gets four. That got fixed in Zen 3 and later, but
> apparently Intel had similar issues (Ivy Bridge: 1 LEA per cycle, vs 3
> "mov i,r". Haswell is 1:4).
Yes, this is the case. I just missed your reply when replying to
Peter's mail with a not so precise answer.
Uros.
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