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Message-ID: <a387837d-e1d1-4101-9e2a-a51d254a428c@kernel.org>
Date: Sun, 6 Oct 2024 15:33:26 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Andrei Stefanescu <andrei.stefanescu@....nxp.com>,
Conor Dooley <conor@...nel.org>
Cc: Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Chester Lin <chester62515@...il.com>,
Matthias Brugger <mbrugger@...e.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
"Rafael J. Wysocki" <rafael@...nel.org>, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, NXP S32 Linux Team <s32@....com>,
Christophe Lizzi <clizzi@...hat.com>, Alberto Ruiz <aruizrui@...hat.com>,
Enric Balletbo <eballetb@...hat.com>
Subject: Re: [PATCH v4 2/4] dt-bindings: gpio: add support for NXP S32G2/S32G3
SoCs
On 04/10/2024 13:10, Andrei Stefanescu wrote:
>
> Just to confirm that I got it right, SIUL2 would end up being a single node,
> looking something like:
>
>
> siul2: siul2@...9c000 {
> compatible = "nxp,s32g2-siul2";
> reg = <0x4009C000 SIUL2_0_SIZE>,
> <0x44010000 SIUL2_1_SIZE>;
> gpio-controller;
> #gpio-cells = <2>;
> gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>;
> gpio-reserved-ranges = <102 10>, <123 21>;
> interrupt-controller;
> #interrupt-cells = <2>;
> interrupts = <GIC_SPI ..>;
>
> /* for nvmem */
> #address-cells = <1>;
> #size-cells = <1>;
>
> *-nvmem-*@...ex {
> reg = <index 0x4>;
> [..]
This looks like using deprecated binding. Switch to the non-deprecated
cells.
Best regards,
Krzysztof
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