linux-kernel - Re: [PATCH v10 06/14] RISC-V: define the elements of the VCSR vector CSR

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Message-ID: <CAFTtA3M3NhooM5u7woDO3juAgQK=EpF-aSf69VJm30aj7iNfZA@mail.gmail.com>
Date: Mon, 7 Oct 2024 00:04:18 +0800
From: Andy Chiu <andybnac@...il.com>
To: Charlie Jenkins <charlie@...osinc.com>
Cc: Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Jisheng Zhang <jszhang@...nel.org>, Chen-Yu Tsai <wens@...e.org>, 
	Jernej Skrabec <jernej.skrabec@...il.com>, Samuel Holland <samuel@...lland.org>, 
	Samuel Holland <samuel.holland@...ive.com>, Jonathan Corbet <corbet@....net>, 
	Shuah Khan <shuah@...nel.org>, Guo Ren <guoren@...nel.org>, Evan Green <evan@...osinc.com>, 
	Andy Chiu <andy.chiu@...ive.com>, Jessica Clarke <jrtc27@...c27.com>, 
	Andrew Jones <ajones@...tanamicro.com>, linux-riscv@...ts.infradead.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-sunxi@...ts.linux.dev, linux-doc@...r.kernel.org, 
	linux-kselftest@...r.kernel.org, Heiko Stuebner <heiko@...ech.de>, 
	Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH v10 06/14] RISC-V: define the elements of the VCSR vector CSR

Charlie Jenkins <charlie@...osinc.com> 於 2024年9月12日 週四 下午1:57寫道：
>
> From: Heiko Stuebner <heiko@...ech.de>
>
> The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].
>
> Define constants for those to access the elements in a readable way.
>
> Acked-by: Guo Ren <guoren@...nel.org>
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@...ll.eu>
> Signed-off-by: Charlie Jenkins <charlie@...osinc.com>

Reviewed-by: Andy Chiu <andybnac@...il.com>

> ---
>  arch/riscv/include/asm/csr.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 25966995da04..3eeb07d73065 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -300,6 +300,10 @@
>  #define CSR_STIMECMP           0x14D
>  #define CSR_STIMECMPH          0x15D
>
> +#define VCSR_VXRM_MASK                 3
> +#define VCSR_VXRM_SHIFT                        1
> +#define VCSR_VXSAT_MASK                        1
> +
>  /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
>  #define CSR_SISELECT           0x150
>  #define CSR_SIREG              0x151
>
> --
> 2.45.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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