linux-kernel - Re: [PATCH v3 1/2] drm: Fix fault format

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <0a419a1d-6124-411c-bcae-a8dac87f73d0@csgroup.eu>
Date: Mon, 7 Oct 2024 08:10:36 +0200
From: Christophe Leroy <christophe.leroy@...roup.eu>
To: Arnd Bergmann <arnd@...db.de>,
 Vincenzo Frascino <vincenzo.frascino@....com>, linux-kernel@...r.kernel.org,
 Linux-Arch <linux-arch@...r.kernel.org>, linux-mm@...ck.org
Cc: Andy Lutomirski <luto@...nel.org>, Thomas Gleixner <tglx@...utronix.de>,
 "Jason A . Donenfeld" <Jason@...c4.com>,
 Michael Ellerman <mpe@...erman.id.au>, Nicholas Piggin <npiggin@...il.com>,
 Naveen N Rao <naveen@...nel.org>, Ingo Molnar <mingo@...hat.com>,
 Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>,
 "H. Peter Anvin" <hpa@...or.com>, Theodore Ts'o <tytso@....edu>,
 Andrew Morton <akpm@...ux-foundation.org>,
 Steven Rostedt <rostedt@...dmis.org>, Masami Hiramatsu
 <mhiramat@...nel.org>, Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
Subject: Re: [PATCH v3 1/2] drm: Fix fault format

Le 04/10/2024 à 15:21, Arnd Bergmann a écrit :
> On Thu, Oct 3, 2024, at 15:29, Vincenzo Frascino wrote:
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
>> b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index a6c69a706fd7..352ef5e1c615 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -308,7 +308,7 @@ static void gen6_check_faults(struct intel_gt *gt)
>>   		fault = GEN6_RING_FAULT_REG_READ(engine);
>>   		if (fault & RING_FAULT_VALID) {
>>   			gt_dbg(gt, "Unexpected fault\n"
>> -			       "\tAddr: 0x%08lx\n"
>> +			       "\tAddr: 0x%08x\n"
>>   			       "\tAddress space: %s\n"
>>   			       "\tSource ID: %d\n"
>>   			       "\tType: %d\n",
> 
> Isn't the type of PAGE_MASK still architecture dependent?

Indeed when I commented that PAGE_MASK was type agnostic I was thinking 
about the powerpc PAGE_MASK:

#define PAGE_MASK      (~((1 << PAGE_SHIFT) - 1))

It should probably be possible to generalise it to all architectures.

But if you keep some PAGE_MASK with forced UL type just like:

#define PAGE_SIZE		(_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK		(~(PAGE_SIZE-1))

Then that version of PAGE_MASK isn't agnostic and ANDing an int with 
that mask makes a long result.

> I think you need a cast to either 'int' or 'long' here to
> make the corresponding format string work across all
> architectures. With the current version of your patch 2/2,
> it looks like it has to be %x for architectures with
> 64-bit phys_addr_t, but %lx for the other ones.
> 
> Changing the 'u32 fault' variable to 'unsigned long'
> would also work here.
> 
>        Arnd