lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [day] [month] [year] [list]
Message-ID: <cd76a15e-70e9-4abf-9932-38d520b66205@gmail.com>
Date: Mon, 7 Oct 2024 10:46:50 +0100
From: "Colin King (gmail)" <colin.i.king@...il.com>
To: Kevin Tang <kevin3.tang@...il.com>
Cc: Kevin Tang <kevin.tang@...soc.com>, Orson Zhai <orsonzhai@...il.com>,
 Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
 "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: shift and mask issue in drivers/gpu/drm/sprd/megacores_pll.c

Hi,

I noticed a shift/mask issue in dphy_set_pll_reg() in 
drivers/gpu/drm/sprd/megacores_pll.c, the expression (pll->kint << 4) & 
0xf is
always zero:

         ...
         reg_val[4] = pll->kint >> 12;
         reg_val[5] = pll->kint >> 4;
         reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);
         ...

I'm not sure what the correct expression should be, but the current 
assignment to reg_val[6] seems incorrect to me.

Colin






Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ