linux-kernel - RE: [PATCH 3/6] drm/exynos: exynos7_drm_decon: fix ideal

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Message-ID: <000001db18a5$125e9320$371bb960$@samsung.com>
Date: Mon, 7 Oct 2024 19:38:39 +0900
From: 대인기/Tizen Platform Lab(SR)/삼성전자
	<inki.dae@...sung.com>
To: "'Kaustabh Chakraborty'" <kauschluss@...root.org>, "'Seung-Woo Kim'"
	<sw0312.kim@...sung.com>, "'Kyungmin Park'" <kyungmin.park@...sung.com>,
	"'David Airlie'" <airlied@...il.com>, "'Simona Vetter'" <simona@...ll.ch>,
	"'Krzysztof Kozlowski'" <krzk@...nel.org>, "'Alim Akhtar'"
	<alim.akhtar@...sung.com>, "'Maarten Lankhorst'"
	<maarten.lankhorst@...ux.intel.com>, "'Maxime Ripard'" <mripard@...nel.org>,
	"'Thomas Zimmermann'" <tzimmermann@...e.de>, "'Rob Herring'"
	<robh@...nel.org>, "'Conor Dooley'" <conor@...nel.org>
Cc: <dri-devel@...ts.freedesktop.org>,
	<linux-arm-kernel@...ts.infradead.org>, <linux-samsung-soc@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: RE: [PATCH 3/6] drm/exynos: exynos7_drm_decon: fix ideal_clk by
 converting it to Hz



> -----Original Message-----
> From: Kaustabh Chakraborty <kauschluss@...root.org>
> Sent: Friday, September 20, 2024 12:11 AM
> To: Inki Dae <inki.dae@...sung.com>; Seung-Woo Kim
> <sw0312.kim@...sung.com>; Kyungmin Park <kyungmin.park@...sung.com>; David
> Airlie <airlied@...il.com>; Simona Vetter <simona@...ll.ch>; Krzysztof
> Kozlowski <krzk@...nel.org>; Alim Akhtar <alim.akhtar@...sung.com>;
> Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>; Maxime Ripard
> <mripard@...nel.org>; Thomas Zimmermann <tzimmermann@...e.de>; Rob Herring
> <robh@...nel.org>; Conor Dooley <conor@...nel.org>
> Cc: dri-devel@...ts.freedesktop.org; linux-arm-kernel@...ts.infradead.org;
> linux-samsung-soc@...r.kernel.org; linux-kernel@...r.kernel.org;
> devicetree@...r.kernel.org; Kaustabh Chakraborty <kauschluss@...root.org>
> Subject: [PATCH 3/6] drm/exynos: exynos7_drm_decon: fix ideal_clk by
> converting it to Hz
> 
> The clkdiv values are incorrect as ideal_clk is in kHz and the clock
> rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.
> 
> Signed-off-by: Kaustabh Chakraborty <kauschluss@...root.org>
> ---
>  drivers/gpu/drm/exynos/exynos7_drm_decon.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> index 2c4ee87ae6ec..4e4ced50ff15 100644
> --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> @@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx)
>  static u32 decon_calc_clkdiv(struct decon_context *ctx,
>  		const struct drm_display_mode *mode)
>  {
> -	unsigned long ideal_clk = mode->clock;
> +	unsigned long ideal_clk = mode->clock * 1000;

Right. ideal_clk should be fixed with Hz.

Thanks,
Inki Dae

>  	u32 clkdiv;
> 
>  	/* Find the clock divider value that gets us closest to ideal_clk
> */
> 
> --
> 2.46.1