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Message-Id: <20241007133115.1482619-7-l.rubusch@gmail.com>
Date: Mon, 7 Oct 2024 13:31:13 +0000
From: Lothar Rubusch <l.rubusch@...il.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
dinguyen@...nel.org,
marex@...x.de,
s.trumtrar@...gutronix.de
Cc: l.rubusch@...il.com,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 6/8] ARM: dts: socfpga: update Enclustra Mercury+ AA1
Introduce support for Enclustra's Mercury+ AA1 SoM, based on Intel
Arria10. This is a flexible approach to allow for combining SoM
with carrier board .dtsi and boot-mode .dtsi in a device-tree file.
Signed-off-by: Andreas Buerkler <andreas.buerkler@...lustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@...il.com>
---
.../devicetree/bindings/arm/altera.yaml | 3 +
.../socfpga/socfpga_arria10_mercury_aa1.dtsi | 141 +++++++++++++++---
2 files changed, 123 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 31af6859d..51f10ff8e 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -32,6 +32,9 @@ properties:
items:
- enum:
- enclustra,mercury-pe1
+ - enclustra,mercury-aa1-pe1
+ - enclustra,mercury-aa1-pe3
+ - enclustra,mercury-aa1-st1
- google,chameleon-v3
- const: enclustra,mercury-aa1
- const: altr,socfpga-arria10
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi
index 41f865c8c..cdd693cf9 100644
--- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1.dtsi
@@ -7,12 +7,14 @@
/ {
- model = "Enclustra Mercury AA1";
- compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
+ model = "Enclustra Mercury+ AA1";
+ compatible = "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
aliases {
ethernet0 = &gmac0;
serial1 = &uart1;
+ spi0 = &qspi;
};
memory@0 {
@@ -24,52 +26,102 @@ memory@0 {
chosen {
stdout-path = "serial1:115200n8";
};
+
+ /* Adjusted the i2c labels to use generic base-board dtsi files for
+ * Enclustra Arria10 and Cyclone5 SoMs.
+ *
+ * The set of i2c0 and i2c1 labels defined in socfpga_cyclone5.dtsi and in
+ * socfpga_arria10.dtsi do not allow for using the same base-board .dtsi
+ * fragments. Thus define generic labels here to match the correct i2c
+ * bus in a generic base-board .dtsi file.
+ */
+ soc {
+ i2c_encl: i2c@...02300 {
+ };
+ i2c_encl_fpga: i2c@...02200 {
+ };
+ };
+};
+
+&i2c_encl {
+ status = "okay";
+ i2c-sda-hold-time-ns = <300>;
+ clock-frequency = <100000>;
+
+ atsha204a: atsha204a@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+
+ isl12022: isl12022@6f {
+ compatible = "isil,isl12022";
+ reg = <0x6f>;
+ };
+};
+
+&i2c_encl_fpga {
+ i2c-sda-hold-time-ns = <300>;
+ status = "disabled";
};
&gmac0 {
+ status = "okay";
phy-mode = "rgmii";
phy-addr = <0xffffffff>; /* probe for phy addr */
-
max-frame-size = <3800>;
-
phy-handle = <&phy3>;
+ /delete-property/ mac-address;
+
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy3: ethernet-phy@3 {
- txd0-skew-ps = <0>; /* -420ps */
- txd1-skew-ps = <0>; /* -420ps */
- txd2-skew-ps = <0>; /* -420ps */
- txd3-skew-ps = <0>; /* -420ps */
+ reg = <3>;
+
+ /* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
+ rxc-skew-ps = <1680>; /* 780ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
- txen-skew-ps = <0>; /* -420ps */
- txc-skew-ps = <1860>; /* 960ps */
rxdv-skew-ps = <420>; /* 0ps */
- rxc-skew-ps = <1680>; /* 780ps */
- reg = <3>;
+
+ /* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
+ txc-skew-ps = <1860>; /* 960ps */
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ txen-skew-ps = <0>; /* -420ps */
};
};
};
-&i2c1 {
- atsha204a: crypto@64 {
- compatible = "atmel,atsha204a";
- reg = <0x64>;
- };
+&gpio0 {
+ status = "okay";
+};
- isl12022: isl12022@6f {
- compatible = "isil,isl12022";
- reg = <0x6f>;
- };
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "disabled";
+};
+
+&uart1 {
+ status = "okay";
};
/* Following mappings are taken from arria10 socdk dts */
&mmc {
+ status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
@@ -79,3 +131,50 @@ &mmc {
&osc1 {
clock-frequency = <33330000>;
};
+
+&eccmgr {
+ sdmmca-ecc@...c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ flash0: s25fl512s@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25fl512s", "jedec,spi-nor";
+ reg = <0>;
+
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ spi-max-frequency = <10000000>;
+
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partition@raw {
+ label = "Flash Raw";
+ reg = <0x0 0x4000000>;
+ };
+ };
+};
+
+&watchdog1 {
+ status = "disabled";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
--
2.25.1
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