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Message-ID: <2fad1566-49f9-4586-b0d4-8a4a12f9e69e@denx.de> Date: Mon, 7 Oct 2024 15:54:26 +0200 From: Marek Vasut <marex@...x.de> To: Gatien Chevallier <gatien.chevallier@...s.st.com>, Olivia Mackall <olivia@...enic.com>, Herbert Xu <herbert@...dor.apana.org.au>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Alexandre Torgue <alexandre.torgue@...s.st.com> Cc: Uwe Kleine-König <u.kleine-koenig@...gutronix.de>, Lionel Debieve <lionel.debieve@...s.st.com>, linux-crypto@...r.kernel.org, devicetree@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Yang Yingliang <yangyingliang@...wei.com> Subject: Re: [PATCH 2/4] hwrng: stm32 - implement support for STM32MP25x platforms On 10/7/24 3:27 PM, Gatien Chevallier wrote: > Implement the support for STM32MP25x platforms. On this platform, a > security clock is shared between some hardware blocks. For the RNG, > it is the RNG kernel clock. Therefore, the gate is no more shared > between the RNG bus and kernel clocks as on STM32MP1x platforms and > the bus clock has to be managed on its own. > > Signed-off-by: Gatien Chevallier <gatien.chevallier@...s.st.com> A bit of a higher-level design question -- can you use drivers/clk/clk-bulk.c clk_bulk_*() to handle all these disparate count of clock easily ?
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